---
title: "Saurav Gupta - FPGA Engineer in Bengaluru | Tal"
description: "Meet Saurav Gupta, FPGA Engineer | M.Tech IIT Bombay | I help build Hardware accelerators | Generalist | Wildlife enthusiast based in Bengaluru. AI stack includes claude code and cursor. Explore public work links including github and youtube.com."
image: "https://tal.club/meet/saurav-gupta-2/share-image"
---

# Saurav Gupta on Tal

## Headline

FPGA Engineer \| M\.Tech IIT Bombay \| I help build Hardware accelerators \| Generalist \| Wildlife enthusiast

## About

I specialise in designing hardware accelerators\. I build high\-performance FPGA\-based trading connectivity solutions that enable ultra\-low\-latency execution for market makers\. I have worked as a Systems Engineer for the Computer Vision Processor in Qualcomm's EVA Systems team where I focused on developing hardware architecture for feature extractors used in various CV use cases like Motion Estimation, Object Tracking etc\. I have worked both as an individual contributor as well as a technical lead and have more than 9 years of experience\. My background includes roles as a Systems Performance Engineer and RTL Designer for Camera ISP\. I am adept in Hardware Systems Design, Functional Modelling, FPGA Implementation, Hardware Programming Languages such as Verilog and VHDL, and High\-Level Synthesis \(HLS\)\. Let's talk if you're interested in discussing or building power\-efficient hardware accelerators or hardware design in general\.

## Location

Bengaluru

## AI stack

claude code

cursor

## Work experience

FPGA Engineer at Optiver, Oct 2025 \- Present · 11 mo, Mumbai

Senior Lead Engineer at Qualcomm, Dec 2022 \- Sep 2025 · 2 y 9 mo, Bengaluru, Karnataka, India · Hybrid, Systems Engineer \- Engine for Visual Analytics \(EVA\) Hardware In my role as a Systems Engineer for EVA at Qualcomm, I focus on developing hardware accelerators for computer vision applications, particularly feature extractors\. My key responsibilities include: 1\. Exploring and evaluating computer vision algorithms for extended reality \(AR, VR\), mobile, and automotive applications\. 2\. Designing and architecting hardware systems to support these algorithms\. 3\. Creating bit exact functional models of computer vision algorithms to be implemented in hardware\. 4\. Collaborating with design verification \(DV\) teams, hardware designers, and performance specialists to deliver low\-power, high\-performance chipsets\.

Senior Engineer at Qualcomm, Jun 2022 \- Nov 2022 · 6 mos, Bengaluru, Karnataka, India · Hybrid, XR R&D Team Computer Vision Algorithms for XR Application Functional Modeling for CV algorithms \(to be Hardened\)

Senior Engineer at Qualcomm, Jul 2020 \- May 2022 · 1 yr 11 mos, Bengaluru, Karnataka, India · Hybrid, Camera Performance \- Spectra ISP As part of the Spectra ISP team, I contributed to enhancing camera performance for Qualcomm Snapdragon SoCs\. My key responsibilities included: 1\. Analyzing and optimizing camera performance for Snapdragon System\-on\-Chips \(SoCs\)\. 2\. Developing performance models for camera Image Signal Processors \(ISPs\)\. 3\. Creating comprehensive performance test plans for both pre\-silicon and post\-silicon verification stages\.

Associate Staff Engineer at Samsung Electronics, Mar 2020 \- Jul 2020 · 5 mos, Bengaluru, Karnataka, Multimedia Design Team In my role within the Multimedia Design Team, I was responsible for the development and integration of advanced multimedia components for Samsung Exynos SoCs\. Key tasks and responsibilities involved: 1\. Developing digital color processing IPs\. 2\. RTL coding using SystemVerilog and High\-Level Synthesis \(HLS\)\. 3\. Integrating Multimedia blocks in the SoC\. 4\. Debugging and resolving sanity issues, including DRC checks like CDC and lint\. 5\. Performing synthesis, Design for Test \(DFT\), and Unified Power Format \(UPF\) tasks for multimedia blocks\.

Senior Engineer at Samsung Electronics, May 2018 \- Mar 2020 · 1 yr 11 mos, Bangalore, Modem Development Team As a member of the Modem Development Team, I contributed to the development and integration of modem blocks for Samsung Exynos SoCs\. Key tasks and responsibilities included: 1\. Developing compression IPs for modems\. 2\. Integrating modem blocks in the SoCs\. 3\. RTL design using SystemVerilog\. 4\. Collaborating with the design verification \(DV\) team to review test plans and coverage

SoC Design Engineer at Intel Corporation, Jul 2017 \- Apr 2018 · 10 mos, Bangalore, Scalable Performance CPU Development Group \(SDG\) 1\. Worked on Integration of UPI Subsystem for Intel's Server SoCs

## Education

Master of Technology \(M\.Tech\.\), Microelectronics, Indian Institute of Technology, Bombay

Bachelor of Engineering \(B\.E\.\), electronics and telecommunication engineering, Jadavpur University

## Public links

- github: https://github\.com/sauravgupta139
- youtube\.com: https://youtube\.com/@strength\_respects\_strength

[View the original profile](https://tal.club/meet/saurav-gupta-2)

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