---
title: "Sathvik Anand Rao - Design Engineer - 1 in Greater Bengaluru Area | Tal"
description: "Meet Sathvik Anand Rao, Design Engineer @ Cadence (SSG – PCIe) | VLSI Design and Verification | Wordsmith | President - TEDxDSCE based in Greater Bengaluru Area. AI stack includes claude, github copilot, and hermes agent."
image: "https://tal.club/meet/sathvik-r/share-image"
---

# Sathvik Anand Rao on Tal

## Headline

Design Engineer @ Cadence \(SSG – PCIe\) \| VLSI Design and Verification \| Wordsmith \| President \- TEDxDSCE

## About

Unlock more of my world here: https://linktr\.ee/vikrao I am a Design Engineering Intern at Cadence Design Systems, in the Silicon Solutions Group \(SSG\), PCIe Gen6 verification team\. My work focuses on UVM/SystemVerilog testbench development, debugging high\-speed protocol components, and end\-to\-end verification across PCIe layers and interfaces\. I am also gaining hands\-on exposure to Functional Safety \(FuSa\), applying methodologies aligned with ISO 26262 to ensure robust and safety\-compliant semiconductor designs\. As a recent Electronics and Communication Engineering graduate, I bring a strong technical foundation in RTL design, verification, and system\-level modeling\. My academic journey included projects ranging from a Network\-on\-Chip for efficient interconnects to AI/ML\-driven embedded systems for autonomous navigation and predictive diagnostics, which broadened my perspective on hardware\-software co\-design\. Beyond technical work, I thrive in leadership and communication roles, having served as Secretary of IEEE\-CEDA and leading initiatives that built VLSI\-focused communities\. I’ve also headed student societies like QuizSoc and LitSoc, sharpening my analytical and public\-speaking skills\. Looking ahead, I aim to grow into roles where I can work at the forefront of next\-generation computing architectures, advanced verification, and AI\-driven validation techniques, steadily contributing to innovations shaping the future of VLSI\.

## Location

Greater Bengaluru Area

## AI stack

claude

github copilot

hermes agent

hugging face

langgraph

OpenRouter

## Work experience

Design Engineer \- 1 at Cadence, Jul 2026 \- Present · 4 mos, Greater Bengaluru Area

President at TEDxDSCE, Jan 2026 \- Present · 10 mos

Intern \- Design Engineering at Cadence, Aug 2025 \- Jul 2026 · 1 yr, Greater Bengaluru Area

Student PGM Chair \- \(IEEE\-DSCE\) at IEEE BANGALORE SECTION, Mar 2025 \- Jul 2025 · 5 mos

Engineering Trainee at Cadence, Feb 2025 \- Jul 2025 · 6 mos

Chapter Secretary at IEEE Council on Electronic Design Automation, Jul 2024 \- Nov 2025 · 1 yr 5 mos, Bangalore Urban, Karnataka, India

Crew Member at IEEE Council on Electronic Design Automation, Apr 2024 \- Jul 2024 · 4 mos

Member at IEEE, Feb 2023 \- Dec 2025 · 2 yrs 11 mos

Member at IEEE BANGALORE SECTION, Feb 2023 \- Jul 2025 · 2 yrs 6 mos

## Education

Bachelor of Engineering \- BE, Electronics and Communications Engineering, Dayananda Sagar College of Engineering, BANGALORE

High School Diploma, Central Board of Secondary Education \(CBSE\)

[View the original profile](https://tal.club/meet/sathvik-r)

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