---
title: "Sathvik Kumar Pamu - Joint Secretary in Greater Hyderabad Area | Tal"
description: "Meet Sathvik Kumar Pamu, Aspiring Design & Verification Engineer | IETE CLUB SECRETARY | Selected in 1 TOPS | Intern@ SSIT | Gate EC’2026 qualified based in Greater Hyderabad Area. AI stack includes claude code, claude, and gemini. Explore public work links including github and sathvikkumarpamu.lov..."
image: "https://tal.club/meet/sathvik-kumar-pamu/share-image"
---

# Sathvik Kumar Pamu on Tal

## Headline

Aspiring Design & Verification Engineer \| IETE CLUB SECRETARY \| Selected in 1 TOPS \| Intern@ SSIT \| Gate EC’2026 qualified

## About

VLSI Design and Verification Aspirant passionate about building silicon from the ground up from RTL to tapeout\-ready design\. Currently part of Team AeroSoC, contributing to GARUDA , a custom RV32IM System\-on\-Chip built collaboratively across the team\. Working on GARUDA has given me hands\-on experience with real\-world digital design challenges — debugging complex systems, working within tight timing and area constraints, and learning how individual subsystems come together into a functioning SoC\. My interests center on: 🔹 Digital design and VLSI verification 🔹 SystemVerilog and UVM methodology 🔹 Collaborative, team\-driven chip design , GARUDA has taught me as much about working across a design team as it has about the silicon itself\. Currently pursuing Final Year B\.Tech in Electronics and Communication Engineering at CVR College of Engineering\. Open to opportunities in VLSI design, digital verification, and semiconductor engineering\. Always happy to connect with others working in chip design — feel free to reach out\.

## Location

Greater Hyderabad Area

## AI stack

claude code

claude

gemini

openai

## Work experience

Joint Secretary at IETE SF CVR, Aug 2025 \- Present · 1 yr 2 mos, Serving as Joint Secretary of the IETE student Forum, supporting the coordination and smooth functioning of chapter activities alongside the executive committee\. Key responsibilities: \- Assist in planning and organizing technical events, workshops, and seminars for chapter members, coordinating logistics and scheduling with faculty advisors and student coordinators\. \- Support member outreach and engagement, helping onboard new members and keep the chapter community active and informed\. \- Liaise between the chapter's leadership and its members to ensure events, deadlines, and initiatives run smoothly\.

Integrated VLSI at SURE TRUST, May 2025 \- Aug 2025 · 4 mos, Vastunagar Rangareddy Telangana, Trained in Digital Design, RTL Design, and ASIC Design Methodologies, with hands\-on exposure to industry\-standard front\-end design flows used in semiconductor development\. Key contributions and learnings: \- Worked on Verilog and SystemVerilog & UVM \-based design and verification exercises, building practical experience with RTL coding, functional simulation, and digital circuit implementation\. \- Gained exposure to semiconductor front\-end design flows, strengthening my understanding of how a design moves from specification to verified RTL\. \- Actively participated in bi\-weekly LST \(Leadership, Skills, and Training\) sessions, which sharpened my communication, teamwork, and problem\-solving abilities alongside the technical curriculum\.

FPGA BASED VLSI DESIGN at Sense Semiconductor & IT Solutions Pvt\. Ltd\., Apr 2025 \- Jun 2025 · 3 mos, Mangalagiri, Gained hands\-on experience in Digital System Design using FPGAs, with a strong focus on Verilog HDL, digital logic design, and RTL implementation building a bridge between theoretical coursework and real\-world hardware design\. Key contributions and learnings: \- Designed and simulated combinational and sequential circuits using Verilog\. \- Implemented core digital building blocks including FSMs, shift registers, counters, and memory modules\. \- Gained exposure to FPGA architecture, static timing analysis, and peripheral interfacing\. \- Worked on a case study involving FIFO design and implementation, applying RTL concepts to a practical, structured design problem\.

Content Creator at IETE SF CVR, Jul 2024 \- Aug 2025 · 1 yr 2 mos, Serving as a Content Creator for the IETE Student Forum, contributing to the chapter's outreach and communication efforts through engaging technical and event\-related content\. Key responsibilities: \- Create content for social media and promotional materials to highlight chapter events, workshops, and technical initiatives, helping boost visibility and member engagement\. \- Collaborate with the executive team to align content with upcoming events, ensuring timely and consistent messaging across platforms\. \- Help build the chapter's online presence, contributing to a more active and engaged student community around IETE's technical activities

## Education

Bachelor of Technology \- BTech, Electronics and Communications Engineering, CVR College of Engineering, Hyderabad

Intermediate, PCM, Acumen Junior College

## Public links

- github: https://github\.com/sathvikkumarpamu
- sathvikkumarpamu\.lovable\.app: https://sathvikkumarpamu\.lovable\.app/

[View the original profile](https://tal.club/meet/sathvik-kumar-pamu)

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