---
title: "Sarthak Varshney - ASIC Digital Design, Engineer in Gurugram | Tal"
description: "Meet Sarthak Varshney, Formal Verification Engineer @Synopsys || Attended VIT VELLORE based in Gurugram. AI stack includes claude, codex, and cursor. Explore public work links including github."
image: "https://tal.club/meet/sarthak-varshney/share-image"
---

# Sarthak Varshney on Tal

## Headline

Formal Verification Engineer @Synopsys \|\| Attended VIT VELLORE

## About

I am currently working as an ASIC Digital Design, Engineer at Synopsys, Bengaluru, where I contribute to IP Verification using Formal Verification\. I have previously worked as a Technical Engineering Intern at Synopsys itself where I developed AMBA APB3 Testbench in SV & UVM with Verification Plan, Architecture, Feature Plan, Assertion Plan, Coverage Plan, etc\. Using the developed Testbench, I explored Synopsys tools & apps like VCS, Verdi, HVP, VSO\.ai and developed scripts using Python & Shell\. I have also contributed in development of C & UVM based Testbench for a SoC where I connected several Verification IPs and also deployed Formal flows like Connectivity, Unreachibility, FRV \(Formal Register Verification\) via AIP\.

## Location

Gurugram

## AI stack

claude

codex

cursor

## Work experience

ASIC Digital Design, Engineer at Synopsys Inc, Jun 2026 \- Present · 5 mos, Hybrid, Formal Verification Engineer

SoC Engineering Intern at Synopsys Inc, May 2025 \- May 2026 · 1 yr 1 mo, On\-site

## Education

Bachelor of Technology \- BTech, Electronics and Communication Engineering, Vellore Institute of Technology

High School Diploma, Non\-Medical \(PCM\), Delhi Public School, Sushant Lok

## Public links

- github: https://github\.com/sarthak301102

[View the original profile](https://tal.club/meet/sarthak-varshney)

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