Headline

Electronics Engineer skilled in VLSI Design and PCB Assembly

About

M.Tech VLSI Design Engineering Student | ASIC Flow | Physical Design | TCAD Simulation As an emerging VLSI Design Engineer, I specialize in translating complex logic into highly optimized silicon. I have a strong foundation in both digital and analog design methodologies, leveraging industry-standard EDA tools to build efficient, power-optimized architectures. Core Competencies & Tools: Design & Flow: RTL Design, FSM-based systems, Complete ASIC Flow (Synthesis to Physical Layout). EDA Tools: Cadence (Genus, Innovus, Virtuoso), Synopsys (DC, ICCII, PrimeTime). Device Modeling: Silvaco TCAD, COMSOL Multiphysics (Focus on GAAFETs and GaN devices). Programming: Verilog, Python, C/C++. Key Milestones: Achieved silicon tapeout for a custom FSM-based voting machine. Executed complete physical design flows for high-speed arithmetic architectures ensuring PPA closure. Published advanced TCAD research in the SST IOP journal and presented at ICONN '25. Currently seeking roles where I can apply my expertise in RTL-to-GDSII flow and device optimization to solve real-world hardware challenges.

Location

Chennai

Work experience

Industrial Trainee at SEMCON ELECTRONICS, Sep 2022 - Oct 2022 · 2 mos, Executed automated PCB assembly and verification processes for energy meter manufacturing.

Intern at Varcons technologies, Aug 2022 - Sep 2022 · 2 mos, Engineered an embedded Smart Parking System integrating microcontrollers and sensors for real-time detection.

Intern at Bionic Engineers, Aug 2021 - Sep 2021 · 2 mos, Designed an IoT-enabled Smart Patient Ward system integrating sensors for real-time health monitoring and automated staff alerts.

Education

Master's degree, VLSI DESIGN, SRM Institute of Science and Technology (SRMIST)

Bachelor of Engineering, Electrical, Electronics and Communications Engineering, Sri Krishna Institute of Technology, Bangalore