---
title: "Saranya Pedapati - Summer Research Fellowship in Tenali | Tal"
description: "Meet Saranya Pedapati, RTL Design Engineer | Verilog/SystemVerilog FPGA | ASIC | Timing Closure | IIT Bombay SRF | Immediate Joiner based in Tenali."
image: "https://tal.club/meet/saranya-pedapati/share-image"
---

# Saranya Pedapati on Tal

## Headline

RTL Design Engineer \| Verilog/SystemVerilog FPGA \| ASIC \| Timing Closure \| IIT Bombay SRF \| Immediate Joiner

## About

RTL Design Engineer with 1 year of experience in FPGA\-based system development, specializing in Verilog/SystemVerilog RTL design, custom IP development, and hardware validation\. Hands\-on experience in designing and implementing RTL modules, FPGA bring\-up, timing closure, and high\-speed data acquisition systems\. Worked with communication protocols including I2C, SPI, UART, and Ethernet\. Strong understanding of ASIC design flow, including synthesis and Static Timing Analysis \(STA\)\. Currently seeking RTL Design opportunities in Hyderabad and available for immediate joining\.

## Location

Tenali

## Work experience

Summer Research Fellowship at Indian Institute of Technology, Bombay, Jun 2024 \- Jul 2024 · 2 mos, Maharashtra, India, Summer Research Fellowship

## Education

Bachelor of Technology \- BTech, Electrical, Electronics and Communications Engineering, Vignan's Foundation for Science, Technology & Research

[View the original profile](https://tal.club/meet/saranya-pedapati)

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