Headline

Design Verification Engineer at Digicomm Semiconductor

About

Verification Engineer with ~2 years of experience in PCIe IP. Strong working knowledge of industry-standard EDA tools including Synopsys VCS, Verdi, and EMAN for simulation, debugging, waveform analysis, and regression management. Strong expertise in | UVM | SystemVerilog/Verilog | Assertions(SVA) | Debugging | Coverage. Experienced in writing reusable verification components and building automation scripts using Python to improve regression efficiency and debug productivity.

Location

Greater Delhi Area

AI stack

claude code

claude

gemini

ChatGPT

Work experience

Design Verification Engineer at Digicomm Semiconductor, Sep 2026 - Oct 2026 · 2 mos, India

Layoff/position eliminated at Career Break, Feb 2026 - Aug 2026 · 7 mos, Noida, Uttar Pradesh, India, I got laid off from SYNOPSYS during their worldwide restructuring phase

IP Verification Engineer (PCIe) at Synopsys Inc, Jun 2024 - Jan 2026 · 1 yr 8 mos, Noida, Uttar Pradesh, India, • Led pre-silicon verification of PCIe4 PHY IP, validating its functionality in UVM-based reusable verification environments, (PCIe IP , UVM) • Enhanced assertion-based verification (SVA) by refining and adding assertions, directly from the protocol spec. , achieving 100% assertion coverage • Executed and analyzed multi-configuration regressions, performed root-cause analysis, raise jira for issue and collaborated with RTL teams to resolve design and testbench issues • Defined verification strategy and contributed to test plan development, ensuring comprehensive coverage of PCIe IP features and corner cases • Debugged compilation and simulation failures, performing R2R and POP testing to ensure regression stability and cross- version tool reliability.Collaborated with RTL teams to understand microarchitecture and debug functional issues. • Reduced incoming customer JIRAs by 10 percent through proactive issue identification, early-stage validation and workflow improvements. • Developed Python scripts to parse regression logs, extract failures, identify trends, and generate consolidated regression summaries using AI. Reduced manual triage effort and improved OST operational efficiency, time taken for reports from 4 hours to less than 2mins.

Intern at 3ST Technologies, Jan 2023 - May 2024 · 1 yr 5 mos, South Extension-I New Delhi, Delhi 110049

Education

B.Tech, Electrical, Electronics and Communications Engineering, Bharati Vidyapeeth's college of engineering

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