Headline

Senior Design Verification Engineer | GPU Pre-Silicon DV | Memory Subsystem | MMU / TLB | Cache Coherency | C++ | SystemVerilog

About

Design Verification Engineer with 6+ years of experience spanning GPU pre-silicon verification, memory-subsystem validation, embedded systems, and storage firmware. My core focus is verification of complex GPU and SoC memory systems, including MMU, TLB, address translation, page-fault handling, cache coherency, and memory virtualization. I work across the verification lifecycle — translating architecture and micro-architecture requirements into verification strategies, developing C++-based test benches and validation utilities, creating directed and constrained-random tests, driving functional coverage closure, analyzing regressions, and performing waveform/RTL-based root-cause debug. I also bring a strong hardware/software background from enterprise SSD development, with hands-on experience in C/C++, ARM M7/R8, ThreadX RTOS, DRAM validation, firmware testing, automation, and low-level hardware/software debugging. Core areas: • GPU / ASIC Design Verification • GPU Memory Subsystem • MMU / TLB / Address Translation • Page Fault & Memory Virtualization Validation • Cache Coherency & Memory-System Verification • C/C++-based Test Benches & Verification Infrastructure • Directed & Constrained-Random Verification • Functional Coverage & Coverage Closure • RTL / Waveform Debug & Regression Triage • RAS / Error Injection / Recovery Validation • C / C++ / Python / Ruby • SystemVerilog | UVM (knowledge) • VCS / Verdi / Jenkins / Git / JIRA

Location

Chikkaballapura

AI stack

gemini

github copilot

Work experience

Senior Design Verification Engineer at Intel, Jan 2024 - Present · 2 yrs 10 mos, Bengaluru, • Drive pre-silicon design verification of complex GPU memory and system features, translating architecture and micro-architecture requirements into verification strategies, test scenarios and coverage goals. • Worked on C/C++-based test benches, test content and validation utilities for simulation-based verification of complex GPU memory-system behavior, corner cases and feature interactions. • Verify memory-management functionality including MMU, TLB, address translation, page-fault handling, cache coherency and memory virtualization. • Develop directed and constrained-random test scenarios to exercise architectural boundaries, negative conditions, corner cases and interactions across memory-system features. • Analyze functional coverage, identify coverage gaps and develop targeted stimulus to drive verification closure, achieving 100% functional coverage on assigned GPU memory-subsystem IPs. • Perform regression triage and waveform-driven RTL debug, correlating test stimulus and observed behavior with specifications to isolate design, test or environment issues and accelerate root-cause analysis. • Validate RAS functionality through error injection, error detection/reporting and hardware recovery-path testing. • Evaluate functional and performance behavior of memory IP against micro-architecture specifications using simulation tracking and waveform analysis. • Collaborate with architecture, RTL design, firmware and driver teams to clarify requirements, debug failures, prioritize issues and drive verification closure.

Senior Product Design Engineer at Western Digital, Aug 2020 - Dec 2023 · 3 yrs 5 mos, Bengaluru, Professionally developed firmware for more than seven Enterprise SSD products, proficient in testing, analysis, debugging, and calibration techniques for NAND Flash and diverse hardware components. Designed and executed real-time embedded firmware solutions for Enterprise SSDs, utilizing C/C++, ARM M7/R8 processors, IPC, and ThreadX RTOS. This innovation allowed for a variety of tests on host-less testers within our organization, resulting in substantial cost savings. Established a self-testing framework to validate the IO path and capture IO performance of Enterprise SSDs, replacing the need for host-IO via PCIe-NVMe, and enabling efficient multiprocessor testing within the drives. Demonstrated expertise in the DRAM subsystem by creating multiple DRAM test frameworks to identify and rectify DRAM failures within Enterprise SSD drives. Devised a framework during the boot-up process to validate flash connectivity, screen NAND for bad blocks, and selectively allocate blocks for file system creation. Resolved drive failures through the utilization of Trace32 Tool and Lauterbach JTAG debugger. Collaborated on the development of an End-to-End Automation framework with Python scripting, batch scripts, Jenkins Tool, and other tools, significantly enhancing regression and firmware testing efficiency, reducing manual effort and engineering hours, and expanding test coverage. Displayed proficiency in various communication protocols, including SPI, I2C/SMBus, UART, and PCIe-NVMe. Actively contributed to code reviews and provided guidance to new hires, ensuring a seamless onboarding and development process

Product Design Engineer Intern at Western Digital, Jan 2020 - Jul 2020 · 7 mos, Bengaluru Area, India, Revamped a company-specific input tool using Python and Qt APIs that facilitated the validation of multiple Enterprise SSD products by coordinating with cross-functional teams in an agile environment.

Teaching Assistant at Birla Institute of Technology and Science, Pilani, Aug 2018 - Dec 2018 · 5 mos, Pilani,India, As a teaching assistant I conduct digital design lab where I educate students regarding different digital circuits and practical implementation of those.

Intern at NTPC Limited, Jun 2017 - Jul 2017 · 2 mos, Talcher Area, India, Worked on the site in conversion process of thermal energy to electrical energy and also transmission of electrical power to different parts of the country.

Member at Indian Society for Technical Education, Aug 2015 - Apr 2017 · 1 yr 9 mos, Bhubaneshwar Area, India

Education

Master of Engineering - MEng, Embedded Systems, Birla Institute of Technology and Science, Pilani

Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering, Silicon Institute of Technology (SIT), Bhubaneswar