---
title: "Samarth Patnaik - Design Verification Engineer in Bhubaneswar | Tal"
description: "Meet Samarth Patnaik, CPU Verification Engineer @Scaledge India Pvt. | RISC-V | Cache Coherency | AXI based in Bhubaneswar."
image: "https://tal.club/meet/samarth-patnaik/share-image"
---

# Samarth Patnaik on Tal

## Headline

CPU Verification Engineer @Scaledge India Pvt\. \| RISC\-V \| Cache Coherency \| AXI

## About

My goal is to build strong expertise in processor architecture and design verification, with a focus on RISC\-V based systems\. I aim to contribute to the development and verification of high\-performance and reliable hardware architectures, while continuously expanding my knowledge in digital design, computer architecture, and verification methodologies\. I am particularly interested in working on modern processor cores, system\-level architectures, and scalable multi\-core platforms\.

## Location

Bhubaneswar

## Work experience

Design Verification Engineer at Scaledge Technology, Sep 2025 \- Present · 9 mos

Design Verification Intern at Scaledge Technology, Jan 2025 \- Sep 2025 · 9 mos

## Education

Bachelor of Technology \- BTech, Electrical, Electronics and Communications Engineering, Silicon Institute of Technology \(SIT\), Bhubaneswar

[View the original profile](https://tal.club/meet/samarth-patnaik)

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