Headline

On Assignment at Meta | Lead Engineer at HCL Tech | Infra Silicon Validation & Automation Testing | Emulation

About

Silicon Validation Engineer at Meta, working on the Infrastructure Silicon Validation team. I specialize in automation testing and validation of IRIS Meta's custom silicon designed to power its infrastructure at scale. My work involves developing and executing automated test frameworks to validate IRIS chip functionality, performance, and reliability, ensuring the silicon meets rigorous quality standards before deployment across Meta's data center fleet. I build and maintain test infrastructure that enables comprehensive coverage of hardware behavior, from pre-silicon verification through post-silicon bring-up and production validation. By combining expertise in hardware validation methodologies with software automation, I help accelerate the silicon development lifecycle and ensure that Meta's custom chips deliver the performance, power efficiency, and reliability required to support billions of users worldwide.

Location

Bengaluru

AI stack

claude code

claude

manus

meta

metaai

openclaw

Work experience

Infra Silicon and Emulation Engineer at Meta Platforms — Infra Silicon Enablement Team, Mar 2026 - Present · 9 mos, Bengaluru, - Worked within Meta's Infra Foundation organization on the Silicon Enablement team, enabling early prototyping, firmware development, and silicon validation for in-house Application-Specific Integrated Circuits (ASICs). - Supported emulation and prototyping workflows using industry-standard platforms (Palladium, Protium, Zebu) for hardware verification and pre-silicon validation. - Collaborated cross-functionally with ASIC design, firmware, and software teams to accelerate silicon bring-up and validation across multiple chip programs (e.g., Artemis, Terminus, Athena, Iris). - Contributed to build tools, CI/CD pipelines, and debugging infrastructure that enabled left-shift validation strategies for Meta's custom silicon. - Worked with hardware interfaces including PCIe and USB for comprehensive hardware validation and testing. - Enabled Meta's mission to deploy domain-specific SoCs that deliver superior compute capacity and efficiency at lower power and cost for AI/ML workloads at scale.

Embedded Design Engineer at HCLTech, May 2025 - Present · 1 yr 7 mos, Bengaluru, On Assignment at Meta Infra Silicon Validation and Automation Testing

Lead Engineer at HCLTech, May 2025 - Present · 1 yr 7 mos

Lead Engineer at HCL Tech, May 2025 - Present · 1 yr 7 mos

Firmware Engineer at Intel India Corporation, May 2025 - Feb 2026 · 10 mos, - Participated in BIOS training sessions covering architecture, configuration, and debugging techniques. - Contributed to BIOS setup and validation for multiple platforms like EDK2, QEMU, and NASM ensuring alignment with project requirements. - Successfully configured BIOS settings for VS Pro and EDK2. - Identified and resolved setup issues during initial deployment. - Created documentation for BIOS setup procedures and troubleshooting. - Deepened understanding of BIOS architecture and boot flow. - Gained hands-on experience with BIOS configuration tools. - Improved debugging and issue resolution skills. - Enhanced collaboration and communication with hardware and firmware teams.

Validation Engineer at Intel India Corporation, Jun 2023 - Jun 2024 · 1 yr 1 mo

Intern at Intel India Corporation, Sep 2022 - May 2023 · 9 mos

Education

MTech, Embedded Systems, Vellore Institute of Technology

Bachelor of Engineering - BE, Computer Engineering, Savitribai Phule Pune University