About
I am an Electronics and Communication Engineering graduate with a strong interest in VLSI Design, RTL Design, and Design Verification. My journey into semiconductor engineering has been driven by a passion for understanding how digital systems are architected, verified, synthesized, and implemented from concept to silicon. Currently, I am gaining hands-on experience as a VLSI Intern at NIELIT CoE, MeitY, where I contribute to digital design and verification learning initiatives while working with industry-standard EDA tools and ASIC design flows. My technical foundation includes Verilog, SystemVerilog, Digital Design, Computer Architecture, and RTL-to-GDSII methodologies. I have worked on end-to-end ASIC projects involving RTL design, functional verification, synthesis, and physical design. Some of my notable projects include the Front-End RTL Design & Verification of a 1x3 Packet Router and the Physical Design & Synthesis of a 500 MHz Synchronous FIFO using Cadence Xcelium, Genus, and Innovus. Through these projects, I have gained practical experience in FSM design, FIFO architectures, timing constraints, waveform debugging, synthesis optimization, and timing closure. My areas of interest include RTL Design, Design Verification, Computer Architecture, SoC Design, AMBA Protocols, and ASIC Implementation. I am continuously expanding my expertise in SystemVerilog, UVM, constrained-random verification, functional coverage, and advanced digital design concepts. After graduating in 2023, I developed strong analytical thinking, discipline, and problem-solving skills through rigorous competitive exam preparation before transitioning fully into VLSI engineering. Today, I am focused on building a career in semiconductor design and verification and am actively seeking opportunities where I can contribute, learn, and grow as an RTL Design or Verification Engineer. I am always open to connecting with professionals, recruiters, and fellow engineers in the semiconductor industry to exchange ideas, learn from experiences, and explore exciting opportunities in VLSI and ASIC Design.
Work experience
Intern at NIELIT-India, Dec 2025 - Present · 7 mos, Noida
Data Science Intern at Learn and Build, May 2022 - Jul 2022 · 3 mos
AI and ML trainee at Edunet Foundation, Aug 2021 - Mar 2022 · 8 mos, India, AI and ML trainee at Tech Saksham program powered by SAP and MICROSOFT and EDUNET FOUNDATION
Content Writer at SPIRIT OF YOUTH FOUNDATION, Sep 2020 - Mar 2021 · 7 mos, Delhi, India, Got this golden opportunity to serve in this non profit organization as an intern learned a lot of things
