Headline

Senior Engineer at Qualcomm

About

Core Competencies : 1. C language 2. Verilog. 3. TCL scripting. 4.Python 5. Perl Familar with .lib/.db , .sdc , .lef , .tf , .tlu+ , .upf, .def Tool expertise : 1. Xilinx Vivado 2. Xilinx SDK 3. Synopsys Icc2 compiler and Prime Time 4. Cadence Virtuoso. 5. S32 Design studio for Arm 6. Cadence Genus for synthesis 7. Model sim 8. Calibre 9. Cadence Innovus

Location

Bengaluru

AI stack

claude code

Work experience

Senior Engineer at Qualcomm, May 2026 - Present · 5 mos, On-site

Senior Physical Design Engineer at Synopsys Inc, Oct 2024 - May 2026 · 1 yr 8 mos, Bengaluru, Karnataka, India

Engineer ll - Physical Design at SmartSoC Solutions Pvt Ltd, Jul 2023 - Sep 2024 · 1 yr 3 mos, Bengaluru, Karnataka, India, -Worked Upon 2.5M Instance Critical Graphics Tiles for AMD Client -Development Activates: Developed Game Changing Graphical User Interface for Managing Tiles

Physical Design Engineer at SmartSoC Solutions Pvt Ltd, Jun 2021 - Jun 2023 · 2 yrs 1 mo, Bengaluru, Karnataka, India, -Implementation of PnR for 5nm 1.5M Instance NB Tiles using ICC2 and caliber for AMD -Developed script's to Automate the issues using TCL -Led a Team to Develop Automatic Presentation with QoR for PnR assessing data using Python

Education

Bachelor of Technology - BTech, Electronics and Communications Engineering, SRM University (Sri Ramaswamy Memorial University)

12th Standard, Maths, Physics and Chemistry, Narayana Institute