EMIR Sign-off Engineer

Bengaluru

Hyderabad, Telangana, India

Hyderabad, Telangana, India

Hyderabad, TG, India

Bengaluru



M.Tech, Electronics
Pondicherry University

Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
Jawaharlal Nehru Technological University
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* Expertise in Power Grid Design, IR Drop Analysis (Static & Dynamic), Chip Power Analysis, Chip Power Design, Power Network Synthesis, EM Analysis (Signal & Power), Power Sign-Off * Expierence in working at 2nm, 6nm, 7nm, 12nm, 16nm, 28nm and 40nm tech nodes for different applications * Expierence in EMIR signoff for various applications like Mobile SOC, Networking SOC, Xbox, Commercial applications like TV, Complex ASIC Memory Controllers, Gaming controllers etc * Expert in setting up & development of EMIR signoff methodology for different business requirements * Expierence in handling with different cross site teams located at different geographical locations * Expierence in leading a team from small projects to multi billion instance count designs. Also expierence in mentoring juniors.
Bengaluru
antigravity
gemini
ASIC SOC EMIR Engineer,Silicon at Google, Aug 2024 - Present · 2 yrs 3 mos, Bengaluru
Staff Engineer ASIC EMIR at Micron Technology, Jul 2021 - Aug 2024 · 3 yrs 2 mos, Hyderabad, Telangana, India, Handling mNAND ASIC Controllers EMIR signoff closure, starting from defining spec to signoff closure. Worked on 12nm to 5nm controllers. Key accomplishments include bring up best in class EMIR methodology include RHCPA package extraction, VCD driven DVD analysis, CTM generation, SH signoff, FIT signoff and other standard signoff checks into execution. Also handled the methodology and automation as per BU requirements for various automotive and industrial applications. Involved in migration of flow from RH to RHSC. Also owning execution of both top and block level EMIR signoff closure, including post silicon activities like DFT experiments etc.
Staff Engineer at Nanopowered, Jan 2021 - Jun 2021 · 6 mos, Hyderabad, Telangana, India, EMIR Signoff activities
System-on-Chip Design Engineer at Intel Corporation, Dec 2018 - Jan 2021 · 2 yrs 2 mos, Hyderabad, TG, India
Senior Engineer at MediaTek, Nov 2017 - Dec 2018 · 1 yr 2 mos, Bengaluru
M.Tech, Electronics, Pondicherry University
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering, Jawaharlal Nehru Technological University