Headline

DSP on SoCs/FPGAs | RTL Design | Custom IP Design | Validation | EW Systems

About

DSP/RTL Engineer with 2 years of experience in Verilog RTL design, FPGA prototyping, synthesis, timing closure, and hardware debug. Proven in delivering synthesizable RTL for complex digital and signal-processing blocks, with strong knowledge of RF receiver systems in Radar and EW domains and experience collaborating across algorithm, hardware, verification, and system teams.

Location

Hyderabad

AI stack

claude code

codex

openai

Work experience

Associate DSP Engineer at CONSTELLI, Jul 2024 - Present · 2 yrs 5 mos

Trainee Intern at CONSTELLI, Jan 2024 - Jun 2024 · 6 mos, Developing Virtual Instruments to implement environments for Radar systems and Telemetry devices.

Winter Mentorship Program at Dyumnin Semiconductors (OPC) Private Limited, Nov 2023 - Jan 2024 · 3 mos, Remote, Developing VIP for serial communication protocols using Cocotb

VLSI Chip Design Intern at Vyorius, Mar 2021 - Jun 2021 · 4 mos, Remote, Learning about various FPGA and ASIC design architectures and developing the DUT for verification of their functionalities.

Education

Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, VNR Vignana Jyothi Institute of Engineering and Technology (VNRVJIET)