---
title: "Sahil Vohra - Senior Custom Layout Engineer in Bengaluru | Tal"
description: "Meet Sahil Vohra, I make Custom Layouts at Velaura AI based in Bengaluru. AI stack includes gemini and openai."
image: "https://tal.club/meet/sahil-vohra/share-image"
---

# Sahil Vohra on Tal

## Headline

I make Custom Layouts at Velaura AI

## About

Results\-driven Standard Cell Layout Staff Engineer with 6 years of expertise in PPA\-optimized layout across cutting\-edge nodes \(down to 2nm\)\. Expert in layout design of complex cells like level shifters and multi bit flops\. Proven success in EM mitigation, designing critical via ladder structures for high\-drive cells, and reducing their layout development time\.

## Location

Bengaluru

## AI stack

gemini

openai

## Work experience

Senior Custom Layout Engineer at Velaura AI, Mar 2026 \- Present · 7 mos, Bengaluru, Senior Custom Layout Engineer at Velaura AI \(formerly Auradine\) through LeadIC Design

Music Producer at Freelance, Apr 2024 \- Mar 2026 · 2 yrs, Produced, mixed and mastered sound tracks for clients and personal social media accounts

Standard Cell Layout, Staff Engineer at Synopsys Inc, Jan 2024 \- Mar 2024 · 3 mos, Hyderabad, \- Led a team of 4 people to design the layouts of EM via ladder for high drive buffers and inverters\.

Standard Cell Layout, Engineer 2 at Synopsys Inc, Jun 2021 \- Dec 2023 · 2 yrs 7 mos, Hyderabad, • Fixed unexpected EM behavior by refining the EM load calculation methodology, thereby solving for unexpected behaviors of EM for high drive cells\. • Defined layout guidelines for EM via ladders based on the findings of the above project, resulting in reduction of layout development time by 80%\.

Standard Cell Layout, Engineer 1 at Synopsys Inc, Feb 2019 \- Jun 2021 · 2 yrs 5 mos, Hyderabad, Telangana, India, • Timely delivered PPA optimized cells built from scratch in cutting edge nodes \(TSMC: 5, 7, Samsung: 4, 8nm\)\. • Handled different types of cell families in the library \(combinational, sequential, AON, filler, level shifters, etc\.\)\. • Have intermediate experience on \(TSMC: 12, 16, 28nm\.\) • Worked on different libraries such as Base, POK, ECO\. • Actively involved in the development of various libraries with architectures such as HS, HD and UHD\. • Fixed pin access in libraries with both unidirectional and bi\-directional metals\. • Parallel project 1 \(Pin position analysis\): Analyzed the impact of, placement of input and output pins on various M0 tracks, on performance of high usage combinational cells \(INV, NAND, NOR, AND, OR\)\.

Technical intern at Synopsys, Dec 2017 \- Feb 2019 · 1 y 2 mo, Hyderabad

## Education

BTech \- Bachelor of Technology, Electronics and Communications Engineering, BML Munjal University

Sacred Heart Convent School

[View the original profile](https://tal.club/meet/sahil-vohra)

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