---
title: "Sagar S Ajjapalar - Intern in Bengaluru | Tal"
description: "Meet Sagar S Ajjapalar, Verilog | RTL Design | Cadence Virtuoso | Xillinx Vivado based in Bengaluru. Explore public work links including github."
image: "https://tal.club/meet/sagar-s-ajjapalar/share-image"
---

# Sagar S Ajjapalar on Tal

## Headline

Verilog \| RTL Design \| Cadence Virtuoso \| Xillinx Vivado

## About

Electronics and Communication Student at Dayananda Sagar Academy of Technology and Management

## Location

Bengaluru

## Work experience

Intern at SURE TRUST, Nov 2025 \- Present · 7 mos, Karnataka, India

## Education

Electronics Engineering, Electrical, Electronics and Communications Engineering, Dayananda Sagar Academy Of Technology And Management, Bangalore

PUC, PCMB, Sri Siddheshwara PU College, Davangere

## Public links

- github: https://github\.com/sagar37\-bot

[View the original profile](https://tal.club/meet/sagar-s-ajjapalar)

```json
{
  "@context": "https://schema.org",
  "@graph": [
    {
      "@type": "Person",
      "@id": "https://tal.club/meet/sagar-s-ajjapalar#person",
      "name": "Sagar S Ajjapalar",
      "url": "https://tal.club/meet/sagar-s-ajjapalar",
      "image": "https://tal.club/meet/sagar-s-ajjapalar/profile-photo.jpg",
      "description": "Meet Sagar S Ajjapalar, Verilog | RTL Design | Cadence Virtuoso | Xillinx Vivado based in Bengaluru. Explore public work links including github.",
      "jobTitle": "Intern",
      "worksFor": {
        "@type": "Organization",
        "name": "SURE TRUST"
      },
      "hasOccupation": {
        "@type": "Occupation",
        "name": "Intern"
      },
      "homeLocation": {
        "@type": "Place",
        "name": "Bengaluru"
      },
      "alumniOf": [
        {
          "@type": "EducationalOrganization",
          "name": "Dayananda Sagar Academy Of Technology And Management, Bangalore"
        },
        {
          "@type": "EducationalOrganization",
          "name": "Sri Siddheshwara PU College, Davangere"
        }
      ],
      "sameAs": [
        "https://github.com/sagar37-bot"
      ],
      "mainEntityOfPage": {
        "@id": "https://tal.club/meet/sagar-s-ajjapalar#webpage"
      }
    },
    {
      "@type": "ProfilePage",
      "@id": "https://tal.club/meet/sagar-s-ajjapalar#webpage",
      "url": "https://tal.club/meet/sagar-s-ajjapalar",
      "name": "Sagar S Ajjapalar on Tal",
      "description": "Meet Sagar S Ajjapalar, Verilog | RTL Design | Cadence Virtuoso | Xillinx Vivado based in Bengaluru. Explore public work links including github.",
      "dateModified": "2026-06-10T13:55:58.874Z",
      "isPartOf": {
        "@id": "https://tal.club/#website"
      },
      "mainEntity": {
        "@id": "https://tal.club/meet/sagar-s-ajjapalar#person"
      },
      "primaryImageOfPage": {
        "@type": "ImageObject",
        "url": "https://tal.club/meet/sagar-s-ajjapalar/profile-photo.jpg",
        "contentUrl": "https://tal.club/meet/sagar-s-ajjapalar/profile-photo.jpg",
        "caption": "Sagar S Ajjapalar profile photo on Tal"
      },
      "inLanguage": "en-IN"
    }
  ]
}
```