Headline

DFT at Google

About

Currently serving as a DFT Engineer at Google, contributing to the development of advanced semiconductor technologies with expertise in VLSI, ASIC, and embedded systems. The focus is on designing and implementing scan and MBIST architectures, preparing simulation environments, and delivering ATE patterns to enhance chip performance and reliability. With over 9 years of experience in design-for-test (DFT) methodologies, the work emphasizes driving operational efficiency and innovation in chip design and testing processes. Proficient in leveraging tools such as Tessent Logic Vision, Synopsys VCS, and Cadence Xrun, ensuring seamless collaboration in developing cutting-edge technologies.

Location

Bengaluru

AI stack

gemini

Work experience

DFT Engineer at Google, Jun 2025 - Present · 1 yr 3 mos, Bengaluru, Karnataka, India

Senior lead DFT engineer at Qualcomm, Nov 2022 - Jun 2025 · 2 yrs 8 mos, Greater Bengaluru Area

Senior DFT engineer at Qualcomm, Dec 2019 - Nov 2022 · 3 yrs, Greater Bengaluru Area

DFT Engineer at Qualcomm, Nov 2018 - Dec 2019 · 1 yr 2 mos, Bengaluru, Karnataka, India

DFT Engineer at Altran, May 2017 - Nov 2018 · 1 yr 7 mos, Bengaluru, Karnataka, India, Client- Qualcomm WTR team

R&T Assistant at NIELIT-India, Aug 2015 - Jun 2016 · 11 mos, Aurangabad,Maharashtra,India, I have assisted professors in conducting Digital IC Design and Device modeling labs

Education

Certified Advanced VLSI Design and Verification course, VLSI Design and Verification, Maven Silicon

M.tech (ELECTRONICS DESIGN AND TECHNOLOGY), Electronics design and technology(VLSI DESIGN), NATIONAL INSTITUTE OF ELECTRONICS & INFORMATION TECHNOLOGY (NIELIT)