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Sachin Seth

Senior Physical Design Engineer at NVIDIA | Ex Intel | IIT Kanpur | वरिष्ठ भौतिक रूप-रेखा अभियंता

Bengaluru

9+ years of work experience

NVIDIA
Mar 20251 yr 9 mosPresent

Bengaluru, Karnataka, India

Team Lead managing a Physical Design team responsible for end-to-end Place-to-GDSII execution of multiple high-performance graphics IP blocks. Lead all aspects of physical implementation, including floorplanning, place and route, power integrity, physical verification, and signoff, while driving execution quality, schedule, and cross-functional collaboration. Mentor and supervise engineers to ensure timely delivery of production-quality silicon. Additionally, lead another team for the development of enterprise AI solutions focused on engineering productivity. Architect and build end-to-end LLM-based applications and agentic AI systems, taking them from concept to production deployment. Deliver AI-driven automation solutions adopted by 500+ engineers, streamlining engineering workflows and accelerating productivity across the organization.
NVIDIA
May 20222 yrs 10 mosFeb 2025

Bengaluru, Karnataka, India

PnR Team Lead for high performance graphics compute
Intel Corporation
Jan 20225 mosMay 2022

Bengaluru, Karnataka, India

Super Section Floorplan Owner on Intel 7 process. Performed initial analysis for partitioning, partition sizing, logic placement, macro planning, feed through routing, metal usage analysis etc for cutting edge high performance compute IP.
Intel Corporation
Jul 20192 yrs 6 mosDec 2021

Bengaluru, Karnataka, India

- Physical design engineer for Graphics IPs on sub-10nm Intel process nodes. - Responsible for Floorplanning of multiblock section as floorplan owner. - Responsible for CTS, Synthesis, Placement and Route (PNR) covergence as an execution owner for complex blocks with multi-voltage domains, multiple clocks, hard and soft macros. - Responsible for timing closure, ECO implementation of sub-10nm blocks. - Developed proficiency in EDA and sign-off tools such as Design Compiler, IC Compiler II, PrimeTime, and internal Intel flows. - Developed strong flow debugging skills. - Thorough understanding of RTL2GDSII flow.
Indian Institute of Technology, Kanpur
Jul 20172 yrsJun 2019

Advanced Centre for Electronics System, IIT Kanpur

Worked with Prof. Sandeep Anand and Prof. S.R Sahoo in the departmental web-page committee for a year. Worked with Prof. Shafi Qureshi and guided graduate and postgraduate students in the project work of the course Analog system design. Worked with Prof. Y S Chauhan as teaching assistant in the course Microelectronics I.

Sachin’s AI Stack

claude code
claude code

Education

INDIAN INSTITUTE OF TECHNOLOGY KANPUR

M.tech, Electrical engineering

INDIAN INSTITUTE OF TECHNOLOGY KANPUR

20172 yrs2019
West Bengal University of Technology, Kolkata

B-tech, Electronics and Communications Engineering

West Bengal University of Technology, Kolkata

20134 yrs2017

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Sachin Seth on Tal

Headline

Senior Physical Design Engineer at NVIDIA | Ex Intel | IIT Kanpur | वरिष्ठ भौतिक रूप-रेखा अभियंता

About

I help make the future possible !

Location

Bengaluru

AI stack

claude code

Work experience

Senior Physical Design Engineer II at NVIDIA, Mar 2025 - Present · 1 yr 9 mos, Bengaluru, Karnataka, India, Team Lead managing a Physical Design team responsible for end-to-end Place-to-GDSII execution of multiple high-performance graphics IP blocks. Lead all aspects of physical implementation, including floorplanning, place and route, power integrity, physical verification, and signoff, while driving execution quality, schedule, and cross-functional collaboration. Mentor and supervise engineers to ensure timely delivery of production-quality silicon. Additionally, lead another team for the development of enterprise AI solutions focused on engineering productivity. Architect and build end-to-end LLM-based applications and agentic AI systems, taking them from concept to production deployment. Deliver AI-driven automation solutions adopted by 500+ engineers, streamlining engineering workflows and accelerating productivity across the organization.

Senior Physical Design Engineer at NVIDIA, May 2022 - Feb 2025 · 2 yrs 10 mos, Bengaluru, Karnataka, India, PnR Team Lead for high performance graphics compute

SoC Design Engineer at Intel Corporation, Jan 2022 - May 2022 · 5 mos, Bengaluru, Karnataka, India, Super Section Floorplan Owner on Intel 7 process. Performed initial analysis for partitioning, partition sizing, logic placement, macro planning, feed through routing, metal usage analysis etc for cutting edge high performance compute IP.

Graphics Hardware Engineer at Intel Corporation, Jul 2019 - Dec 2021 · 2 yrs 6 mos, Bengaluru, Karnataka, India, - Physical design engineer for Graphics IPs on sub-10nm Intel process nodes. - Responsible for Floorplanning of multiblock section as floorplan owner. - Responsible for CTS, Synthesis, Placement and Route (PNR) covergence as an execution owner for complex blocks with multi-voltage domains, multiple clocks, hard and soft macros. - Responsible for timing closure, ECO implementation of sub-10nm blocks. - Developed proficiency in EDA and sign-off tools such as Design Compiler, IC Compiler II, PrimeTime, and internal Intel flows. - Developed strong flow debugging skills. - Thorough understanding of RTL2GDSII flow.

Teaching Assistant at Indian Institute of Technology, Kanpur, Jul 2017 - Jun 2019 · 2 yrs, Advanced Centre for Electronics System, IIT Kanpur, Worked with Prof. Sandeep Anand and Prof. S.R Sahoo in the departmental web-page committee for a year. Worked with Prof. Shafi Qureshi and guided graduate and postgraduate students in the project work of the course Analog system design. Worked with Prof. Y S Chauhan as teaching assistant in the course Microelectronics I.

Education

M.tech, Electrical engineering, INDIAN INSTITUTE OF TECHNOLOGY KANPUR

B-tech, Electronics and Communications Engineering, West Bengal University of Technology, Kolkata