---
title: "Rushikesh Yewahare - Design Verification Engineer in Bengaluru | Tal"
description: "Meet Rushikesh Yewahare, Design Verification Engineer | UVM · System Verilog · Assertions | UART · I2C · APB · AXI | Intel & L&T Semi | Targeting Complex IP & SoC Verification based in Bengaluru. AI stack includes claude and openai."
image: "https://tal.club/meet/rushikesh-yewahare/share-image"
---

# Rushikesh Yewahare on Tal

## Headline

Design Verification Engineer \| UVM · System Verilog · Assertions \| UART · I2C · APB · AXI \| Intel & L&T Semi \| Targeting Complex IP & SoC Verification

## About

I don't just write testbenches — I break designs before silicon does\. With \~3 years verifying digital IPs at Intel and L&T Semiconductor, I've built UVM verification environments from scratch — including sole ownership of APB, UART, and FluxLink IPs and contributed to two successful SoC tapeouts\. I've led functional coverage strategy and closure across a team, in addition to authoring coverage models myself, and closed coverage on protocols like UART, APB, and GPIO\. I've also built checkers and assertions for FluxLink, an inter\-submodule voltage\-domain conversion interface, and worked on mixed\-signal verification of NTC thermistor\-based temperature sensing\. Along the way I've caught RTL bugs that would've been expensive post\-tapeout\. My toolkit: SystemVerilog · UVM · Constrained\-Random Testing · SVA Assertions · Functional Coverage · ASIC Flows · APB · UART · GPIO · FluxLink · VCS · Xcelium · SimVision · imc · AXI \(beginner level, currently building foundational knowledge\) What drives me isn't just closing coverage — it's understanding why a design breaks\. That mindset has helped me debug edge cases others miss and contribute to cleaner sign\-offs\. Actively seeking opportunities in complex IP and SoC verification, where I can contribute to challenging designs and grow toward full\-chip ownership\. 📩 Open to relocation for full\-time roles in India, Singapore, Malaysia, USA, Germany, Ireland, Spain and the Netherlands — requiring visa sponsorship where applicable\. If you're working on cutting\-edge silicon, let's connect\. Feel free to reach out via LinkedIn DM or rushirpatil20@gmail\.com — I respond within 24 hours\.

## Location

Bengaluru

## AI stack

claude

openai

## Work experience

Design Verification Engineer at L&T Semiconductor Technologies, Sep 2024 \- Present · 2 yrs 1 mo, Bengaluru, Karnataka, India, Built end\-to\-end UVM testbenches from scratch for UART, I2C, GPIO, and APB protocols — covering sequence items, drivers, monitors, agents, scoreboards, and full environment architecture aligned with project verification plans\. 🔹 Achieved verification closure through coverage\-driven methodology — combining constrained\-random stimulus, functional coverage, and SVA assertions to eliminate coverage holes and validate corner\-case scenarios\. 🔹 Executed protocol\-level validation across UART \(parity/stop\-bit checks, error injection\), I2C \(ACK/NACK, clock stretching\), and APB \(turnaround cycles, register\-level behavior\) — ensuring zero protocol violations at sign\-off\. 🔹 Debugged complex RTL and testbench failures using SimVision waveforms, simulation logs, and coverage reports — systematically isolating root causes and reducing re\-simulation cycles\. 🔹 Integrated BFMs, virtual interfaces, and reference models for end\-to\-end data path checking — enabling automated scoreboard comparison and reducing manual debug effort\. 🔹 Maintained regression stability across multiple IPs, updated test plans, and collaborated with RTL designers and senior DV engineers for issue tracking and testcase signoff\.

Trainee at Intel Corporation, Jul 2023 \- Jun 2024 · 11 mo, Bengaluru, Karnataka, India, Developed good understanding in FUNCTIONAL COVERAGE & CODE COVERAGE For INTEL SPECIFIC IP’S \. \- Implemented Detail functional coverage plans from the ground up for our IP, ensuring we test every important feature thoroughly\. \-Automation script for Making pearl Score to Display Customers Pearl score of an IP in perl Scripting Language\. \-Reproduced and Debugged Design in Verdi Tool for validating various IP’S\. \-Developed Good Understanding of POWERBI tool for Displaying FUNCTINAL & CODE COVERAGE to Customers\. \- Worked on enabling multi\-vendors simulators\(Questasim\) for SATORI\. \- Worked on IP called Satori on debug of failing test case, root cause and fix for the issue\. Keywords : FUNCTIONAL COVERAGE & CODE COVERAGE, System Verilog, Shell, Verdi , VCS, GVIM Editor\.

## Education

Mtech, Embedded system, Vellore Institute of Technology

Bachelor of Engineering \- BE, Electrical, Electronics and Communications Engineering, Savitribai Phule Pune University

[View the original profile](https://tal.club/meet/rushikesh-yewahare)

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