--- title: "ROHAN PATIL - Principal Engineer in Bengaluru | Tal" description: "Meet ROHAN PATIL, Principal Engineer at Tejas Networks based in Bengaluru. AI stack includes claude code, claude, and cursor." image: "https://tal.club/meet/rohan-patil-3/share-image" --- # ROHAN PATIL on Tal ## Headline Principal Engineer at Tejas Networks ## About 5\+ years of experience in Communications Engineering Experience in analysing issues raised during 3GPP conformance test, customer Field trial, In\-house test and IOT compliance test\. Experience in triple mode platforms and GAP scheduling mechanism where one RAT is master and provides GAPs for slave RATS for IRAT measurements\. Experience in core L1 3G concepts DCH timing state machine, cell search mechanism\. Experience in log analysis and crash dump analysis\. Experience in development of 3GPP physical layer BRP and CRP modules Experience in Architecture Specific Fixed point C coding \(Matlab floating point to fixed point conversion\) Experience in VLIW DSP Assembly coding \( low level programming\) and debugging skills Experience in firmware development of Digital TV standard for a SIMD VLIW processor Experience in complexity analysis and optimizing program and data memory of modules Experience in preparing design and Interface documents Experience in testing and validation of Saankhya Labs Compiler and Assembler Experience in handling Real Time Spectrum Analyzer, Digital Oscilloscope and other Lab instrument ## Location Bengaluru ## AI stack claude code claude cursor deepseek gemini kimi ## Work experience Principal Engineer at Tejas Networks, Aug 2020 \- Aug 2026 · 6 yrs 1 mo, Bengaluru, Karnataka, India Lead Software Engineer at Sasken Communication, Bangalore \(Team acquired from Saankhya Labs, Bangalore\), Dec 2013 \- Aug 2020 · 6 yrs 9 mos, Bangalore, Client: Intel Mobile Communication, Bangalore\. Dec 2013 \- Till date Project Title: UMTS L1 controller\. Description: Development and sustenance of UMTS L1 controller\. Responsibilities: Analysis of message flow, handling data and scheduling events between Access Stratum and 3G Firmware\. Experience in analysing issues raised during 3GPP conformance test, customer Field trial, In\-house test and IOT compliance test and also providing the fix if required\. Working on log analysis and crash dump analysis and also debugging system related issues to find the root cause\. Developed features such as Cell Lock, Fast Cell Search in 3G and Partial Overlap Detection\. Working triple mode platforms\. Good understanding on GAP scheduling mechanism where one RAT is master and provides GAPs for slave RATS for IRAT measurements\. MEMBER TECHNICAL STAFF at Saankhya Labs Pvt\. Ltd\., Jul 2012 \- Nov 2013 · 1 yr 5 mos, bangalore, Project Title: HSPA downlink Receiver Mar 2013 \- Nov 2013 Description: Receiver C model for HSDPA downlink Responsibilities: Development of C code and testing the bit rate processing \(BRP\) modules HS\-SCCH decoder, De\-Interleaver, Rate De\-Matcher, De\-Scrambler, Bit De\-Collection, CRC De\-Attach etc Development of C code and testing the chip rate processing \(CRP\) module Cell Search process Worked on defining Instruction Set Assembler \(ISA\) for development of WCDMA Physical layer Prepared design document and documentation on complexity analysis Project Title: Generic RS decoder Jan 2013 \- Feb 2013 Description: RS codes are block\-based error\-correcting mechanism used in digital transmission and storage Responsibilities: Development of assembly code for Generic Reed Solomon \(RS\) decoder to support all the TV standards like DVBT, ATSC, ATSC\-MH and Universal Cable Standard Integration and testing on in house Pruthvi multi core DSP chip Project Title: Tablet to TV and IP over coax for Consumer Electronic Show \(CES\) Dec 2012 \- Dec 2012 Description: Application of in house Pruthvi Tx and Rx in Tablet to TV and IP over coax project Responsibilities: Development of assembly code to support Null packet insertion for DVBT, ISDBT and Cable\-B Modulator standard for Tablet to TV project Support for IP over coax project Project Title: Modulator for DVB\-T standard July 2012 \- Nov 2012 Description: Transmitter model for DVB\-T standard Responsibilities: Development of Fixed Point C Algorithms for various modules Development of Assembly Language program for the algorithms developed in C Integration, Testing and Validation on using Simulator and in house Pruthvi multi core DSP chip Reduced the code loading time by code optimization Parameter configuration parsing according to DVBT Register Spec Documentation on complexity and signal flow for all the CPU's Software engineer at Vayavya Labs Pvt\. Ltd, Aug 2011 \- Jul 2012 · 1 yr, bangalore, Client: Saankhya Labs Pvt Ltd, Bangalore\. Mar 2012 \- June 2012 Project Title: GI averaging, variance and channel detection in AWGN case in for DVBT demodulator\. Description: Receiver model for DVB\-T standard\. Responsibilities: Development of Fixed point C and Assembly code for Guard Interval\(GI\) averaging, variance and channel detection in AWGN case for Signal Processing CPU\. Integration and testing in whole DVBT demodulator chain\. Client: Saankhya Labs Pvt Ltd, Bangalore\. Aug 2011 \- Mar 2012 Project Title: Testing and validation of Saankhya Labs Tool chain\. Description: Testing and Validation of tools such as JRE tool, Compiler Binutils and GDB\. Responsibilities: Develop test cases and Validation for Saankhya Labs JRE tool, C compiler, Binutils and GDB for DSP Processor\. Involved in GDB scripting to make GDB commands equivalent to SDB commands\. Init code for Signal conditioning CPU common for all the standard for JRE tool\. Electronic Engineer at Aeronotical Development Agency, Aug 2010 \- Aug 2011 · 1 yr 1 mo, bangalore, Worked as a Quality Analyst \(QA\) in DGAQA \(Director General Aeronautical Quality Assurance\) for Electrical and Avionics system for Light Combat Aircraft \(LCA\) project\. RESPONSIBILITIES: Failure mode and effect analysis for different system of electrical and avionics\. Fault tree analysis for different systems of electrical and avionics\. Reliability analysis for different systems of electrical and avionics\. QA coverage and process verification during development phase of different system and sub systems\. ## Education Gomatesh High School Belgaum, Karnataka Gomatesh high school Belgaum [View the original profile](https://tal.club/meet/rohan-patil-3) ```json { "@context": "https://schema.org", "@graph": [ { "@type": "Person", "@id": "https://tal.club/meet/rohan-patil-3#person", "name": "ROHAN PATIL", "url": "https://tal.club/meet/rohan-patil-3", "image": "https://tal.club/meet/rohan-patil-3/profile-photo.jpg", "description": "Meet ROHAN PATIL, Principal Engineer at Tejas Networks based in Bengaluru. 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