Headline

Senior Engineer at Synopsys | Ex SoC Design intern at INTEL | M.Tech NIT Karnataka,Surathkal

About

Welcome! I'm MTech graduate from NIT Karnataka ,currently working in Synopsys as Senior Application Engineer I use to post contents related to VLSI Domain on LinkedIn. I am skilled in C/C++, Verilog and System Verilog. I have interned at INTEL as Validation intern. My objective is to excel in a challenging environment, contributing to self-development and organizational goals in the VLSI domain. Lets connect!!

Location

North Delhi

Work experience

Senior Engineer at Synopsys Inc, Feb 2024 - Present · 2 yrs 5 mos, Hyderabad, Telangana, India

Soc Intern at Intel Corporation, Aug 2022 - May 2023 · 10 mos, Bengaluru, Karnataka, India, Worked on Next Generation chip set for 5G base station • Executed regression testing for register read write functionality. • Coding of Memory(DRAM,IRAM,Shared Memory) Read Write test and tested in Frio System(Combinations:Read write from PCIe,Read Write from core ,Write from PCIe read from core and vice-versa) • Ramped up on Cadence LX7 Xtensa Architecture • Hands-on on Xtensa Xplorer.

Student Intern at Bharat Heavy Electricals Limited, Jun 2019 - Jul 2019 · 2 mos, Noida, Uttar Pradesh, India

Student Intern at Tata Power-DDL, Jun 2018 - Jul 2018 · 2 mos, New Delhi, Delhi, India

Education

Master of Technology - MTech, Electronics and Communications Engineering, National Institute of Technology Karnataka

Bachelor of Technology - BTech, Electronics and Communications Engineering, Bhagwan Parshuram Institute of Technology