Design Verification Aspirant | Advanced VLSI Trainee | SystemVerilog • UVM • RTL Verification | ECE 2025 | MIT Mysore
Bacholar of Engineering - BE in Electronics and communication
Visvesvaraya Technological University
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Download Tal BossDesign Verification Aspirant | Advanced VLSI Trainee | SystemVerilog • UVM • RTL Verification | ECE 2025 | MIT Mysore
Electronics and Communication Engineering graduate (2025) from Maharaja Institute of Technology, Mysore, with strong interest in Design Verification and Digital VLSI. Currently building skills in: • Verilog & SystemVerilog • UVM methodology • RTL design & verification • Functional verification concepts • Digital electronics & computer architecture I am actively seeking opportunities in Design Verification, RTL Verification, and ASIC verification domains where I can contribute, learn, and grow in the semiconductor industry. Open to internships, trainee roles, and entry-level DV opportunities.
Mysore
Currently Trainee @VLSI EXPERT at VLSI EXPERT Private Limited, Jul 2025 - Present · 1 yr
Bacholar of Engineering - BE in Electronics and communication, Visvesvaraya Technological University