---
title: "Ravi Agrahari - DFT Design Engineer in Greater Bengaluru Area | Tal"
description: "Meet Ravi Agrahari, DFT Design Engineer @ Qualcomm | M.Tech in VLSI @ IITJ’25 based in Greater Bengaluru Area. AI stack includes gemini."
image: "https://tal.club/meet/ravi-agrahari/share-image"
---

# Ravi Agrahari on Tal

## Headline

DFT Design Engineer @ Qualcomm \| M\.Tech in VLSI @ IITJ’25

## Location

Greater Bengaluru Area

## AI stack

gemini

## Work experience

DFT Design Engineer at Qualcomm, Sep 2025 \- Present · 1 yr 2 mos, Bengaluru, Karnataka, India, \- Worked on advanced 4nm SoC, owning SAF & TDF DFT ATPG implementation and sign\-off for multiple cores\. ‑ Achieved 99\.3% test coverage for SAF using Siemens Tessent by analyzing and debugging coverage loss\. ‑ Debugged SAF & TDF simulations including SDFMAX, SDFMIN, zero\-delay, PA, and Non\-PA simulations using Synopsys Verdi\. ‑ Resolved DFT DRC violations ensuring clean sign\-off\. ‑ Performed multi\-corner \(PVT\) validation and frequency\-aware TDF analysis across clock domains\. ‑ Supporting MTO tapeout and released validated ATPG patterns to the ATE team for silicon bring\-up and testing, achieving 100% pass rate for both SAF and TDF vectors during the P0 phase\.

## Education

Master of Technology \- MTech, Intelligent VLSI System, Indian Institute of Technology Jodhpur

B\.TECH\(HONS\.\), Electronics and Communication Engineering, Krishna institute of engineering & technology

[View the original profile](https://tal.club/meet/ravi-agrahari)

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