Ravi Agrahari
DFT Design Engineer @ Qualcomm | M.Tech in VLSI @ IITJ’25
Greater Bengaluru Area
1+ year of work experience
Sep 20251 yr 2 mosPresent
Bengaluru, Karnataka, India
- Worked on advanced 4nm SoC, owning SAF & TDF DFT ATPG implementation and sign-off for multiple cores.
‑ Achieved 99.3% test coverage for SAF using Siemens Tessent by analyzing and debugging coverage loss.
‑ Debugged SAF & TDF simulations including SDFMAX, SDFMIN, zero-delay, PA, and Non-PA simulations using Synopsys Verdi.
‑ Resolved DFT DRC violations ensuring clean sign-off.
‑ Performed multi-corner (PVT) validation and frequency-aware TDF analysis across clock domains.
‑ Supporting MTO tapeout and released validated ATPG patterns to the ATE team for silicon bring-up and testing, achieving 100% pass rate for both SAF and TDF vectors during the P0 phase.
Ravi’s AI Stack
Education
Master of Technology - MTech, Intelligent VLSI System
Indian Institute of Technology Jodhpur
20232 yrs2025
B.TECH(HONS.), Electronics and Communication Engineering
Krishna institute of engineering & technology
20174 yrs2021
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