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Ramesh Darwin

ATE Test Engineer

Bengaluru

19+ years of work experience

Cadence
Aug 20251 yr 2 mosPresent

Bengaluru, Karnataka, India

ARM Artisan IP team assimilated into Cadence
Arm
Oct 20195 yrs 11 mosAug 2025

Bengaluru Area, India

• Worked on Physical IP testchip Functional validation , characterization and Reliability testing activities • Characterization involves both AC and DC .Reliability testing involves HTOL and ESD-LU activities • Supported HTOL Burn in board , ESD-LU daughter-card,AC char board design activities . • Hands on expertise in AC char Bench Test setup bring-up • Worked along with design team on Physical FA activities .
Altran
Nov 20181 yrOct 2019

Bangalore Urban, Karnataka, India

Test engineering Consultant @ CISCO through Altran , worked on CISCO IP's Structural validation and Characterization
Anora
Oct 20126 yrs 1 moOct 2018

Bangalore

• Worked on ATPG offline pgm development & Phasing activities for Qualcomm SOC devices & Trained on SMT8 • Worked on Vseries -Fusion & Fusion-A93K Conversion pgm development for TI processor & it’s load board design. debug and production release support • Worked on A580 -A93K Conversion pgm development for the transceiver & it’s Hardware design, Debug, Correlation & Program release. • Worked on NXP Ultra High Voltage Automotive SOC devices & its load board design, Test program development, debug and production release. • Worked on DIB Diagnostic program development and Relay control programming using I2C relay driver.
Tessolve Services Pvt. Ltd.
Aug 20102 yrs 3 mosOct 2012

Bengaluru Area, India

• Worked as Quality engineer for Hardware release across ATE platforms • Performed Test program audit in various phase of project. • Played key role to first pass HW success & ensure Quality product release.
Tessolve Services Pvt. Ltd.
Aug 20073 yrs 3 mosOct 2010

Bangalore

Tester : Verigy 93K • Register Read/write program development and DC Parametric testing for NVIDIA Multi-Chip Processor • Supported ATE Load Board design . • Worked on Structural validation and Characterization of the Qualcomm processors

Ramesh’s AI Stack

claude
claude

Education

B.E, Electrical

K.L.N college of engg ,Anna University

20023 yrs2005

Diploma, Electrical and Electronics Engineering

V.S.V.N .Polytechnic Virudhunagar

19993 yrs2002

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Headline

ATE Test Engineer

About

• 20+ years of relevant work experience in post-silicon validation under the ATE environment. • Involved in program conversions from legacy ATE platform to Road map ATE platform • Product breadth -SOC, Processors, Transceivers, and ASIC devices • Detailed test plan development after understanding the device functionality and test parameters. • Responsible for identification of the tester platform for the device and hardware (Load board) design • To work progressively with the PCB design/CAD team and help in releasing the hardware to FAB. • Expertise in Test program development for the tester platforms Advantest V93K • Experienced in Reliability Testing HTOL and ESD-LU • Very familiar with processes and systems in Test and Product Engineering

Location

Bengaluru

AI stack

claude

Work experience

Principal Test Engineer at Cadence, Aug 2025 - Present · 1 yr 2 mos, Bengaluru, Karnataka, India, ARM Artisan IP team assimilated into Cadence

Staff Test Engineer at Arm, Oct 2019 - Aug 2025 · 5 yrs 11 mos, Bengaluru Area, India, • Worked on Physical IP testchip Functional validation , characterization and Reliability testing activities • Characterization involves both AC and DC .Reliability testing involves HTOL and ESD-LU activities • Supported HTOL Burn in board , ESD-LU daughter-card,AC char board design activities . • Hands on expertise in AC char Bench Test setup bring-up • Worked along with design team on Physical FA activities .

Lead Engineer at Altran, Nov 2018 - Oct 2019 · 1 yr, Bangalore Urban, Karnataka, India, Test engineering Consultant @ CISCO through Altran , worked on CISCO IP's Structural validation and Characterization

Product Development Engineer-II at Anora, Oct 2012 - Oct 2018 · 6 yrs 1 mo, Bangalore, • Worked on ATPG offline pgm development & Phasing activities for Qualcomm SOC devices & Trained on SMT8 • Worked on Vseries -Fusion & Fusion-A93K Conversion pgm development for TI processor & it’s load board design. debug and production release support • Worked on A580 -A93K Conversion pgm development for the transceiver & it’s Hardware design, Debug, Correlation & Program release. • Worked on NXP Ultra High Voltage Automotive SOC devices & its load board design, Test program development, debug and production release. • Worked on DIB Diagnostic program development and Relay control programming using I2C relay driver.

Quality Engineer at Tessolve Services Pvt. Ltd., Aug 2010 - Oct 2012 · 2 yrs 3 mos, Bengaluru Area, India, • Worked as Quality engineer for Hardware release across ATE platforms • Performed Test program audit in various phase of project. • Played key role to first pass HW success & ensure Quality product release.

Test Engineer at Tessolve Services Pvt. Ltd., Aug 2007 - Oct 2010 · 3 yrs 3 mos, Bangalore, Tester : Verigy 93K • Register Read/write program development and DC Parametric testing for NVIDIA Multi-Chip Processor • Supported ATE Load Board design . • Worked on Structural validation and Characterization of the Qualcomm processors

Education

B.E, Electrical, K.L.N college of engg ,Anna University

Diploma, Electrical and Electronics Engineering, V.S.V.N .Polytechnic Virudhunagar