Headline

Senior SRAM Memory Layout Engineer | Advanced Node Expertise (2nm, 3nm and 22nm) | GAAFET, FinFET, and planar CMOS | Custom Design and Automation

About

Senior Memory Layout Engineer with 4+ years of experience in full-custom/compiler SRAM/RF layout at advanced nodes (2nm, 3nm, and 22nm). Skilled in Periphery logic design (Centres, IOs etc.), EMIR fixes, DRC/LVS closure, ERC/DFM compliance, CalQA, PPA optimisation, Matching and Shielding. Experienced in Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre and ICV verification, and cross-domain collaboration with circuit design teams. Keen to expand into Memory Layout/Compiler development and flow automation roles. Open to look for roles that give exposure to strengthening scripting fundamentals (SKILL/Tcl/Python).

Location

Bengaluru

AI stack

claude

gemini

Work experience

Senior Memory Layout Engineer at Broadcom, Feb 2026 - Present · 8 mos, Bengaluru, Karnataka, India

Senior Memory Layout Engineer at UANDWE, Inc., Feb 2026 - Present · 8 mos, Bengaluru, Karnataka, India

Layout Design, Engineer at Synopsys Inc, Oct 2022 - Jan 2026 · 3 yrs 4 mos, Noida, Uttar Pradesh, India

A&MS Layout Design Intern at Synopsys Inc, May 2022 - Sep 2022 · 5 mos, Noida, Uttar Pradesh, India

Research Student at IEEE AP-MTTS SBC, IIT Kharagpur, Aug 2020 - Aug 2020 · 1 mo, Aligarh, Uttar Pradesh, India, I designed and analyzed a THz micro-strip antenna for WBAN (Wireless Body Area Networks) in HFSS. I selected the THz frequency, considering the need for high data rates and scarcity of spectrum. Apart from its compact size and minimum back radiation, the antenna also showed high gain and directivity.

Education

Bachelor of Technology, Electronics Engineering, Aligarh muslim university

Higher Secondary, Mathematics and Science, SAIYYID HAMID SENIOR SECONDARY SCHOOL