---
title: "Nikhil Yadav Ragir - Project Officer II in Hyderabad | Tal"
description: "Meet Nikhil Yadav Ragir, Design Verification Engineer II - IIT Hyderabad | ORAN - 5G/6G based in Hyderabad. AI stack includes openai."
image: "https://tal.club/meet/ragir-nikhil-yadav/share-image"
---

# Nikhil Yadav Ragir on Tal

## Headline

Design Verification Engineer II \- IIT Hyderabad \| ORAN \- 5G/6G

## About

• Design Verification Engineer with 3 YOE in functional verification using SystemVerilog and UVM\. • Experienced in developing reusable UVM testbenches, constrained\-random verification environments, scoreboards, assertions \(SVA\), and functional coverage\. • Hands\-on experience verifying AXI, AHB, APB, I3C, PWM, and ULPI protocols\. • Skilled in verification planning, regression debugging, coverage closure, and RTL debugging while collaborating with design teams to deliver high\-quality silicon\. • Core Skills: SystemVerilog, UVM, Verilog, SVA, Functional Coverage, Constrained\-Random Verification, AXI, AHB, APB, I3C, PWM, ULPI, Linux, Python\.

## Location

Hyderabad

## AI stack

openai

## Work experience

Project Officer II at NG\-RAN IIT Hyderabad, Nov 2025 \- Present · 11 mos, Hyderabad, Telangana, India

Design Verification Engineer I at SmartSoC Solutions Pvt Ltd, Nov 2024 \- Nov 2025 · 1 yr 1 mo, Hyderabad, Telangana, India

Design Verification Engineer I at SmartSoC Solutions Pvt Ltd, Aug 2023 \- Oct 2024 · 1 yr 3 mos, Hubli, Karnataka, India

## Education

Bachelor of Engineering \- BE, Electronics & Communications Engineering, Vasavi College of Engg

Intermediate, MPC, Nano Junior College

[View the original profile](https://tal.club/meet/ragir-nikhil-yadav)

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