Nikhil Yadav Ragir on Tal
Headline
Design Verification Engineer II - IIT Hyderabad | ORAN - 5G/6G
About
• Design Verification Engineer with 3 YOE in functional verification using SystemVerilog and UVM. • Experienced in developing reusable UVM testbenches, constrained-random verification environments, scoreboards, assertions (SVA), and functional coverage. • Hands-on experience verifying AXI, AHB, APB, I3C, PWM, and ULPI protocols. • Skilled in verification planning, regression debugging, coverage closure, and RTL debugging while collaborating with design teams to deliver high-quality silicon. • Core Skills: SystemVerilog, UVM, Verilog, SVA, Functional Coverage, Constrained-Random Verification, AXI, AHB, APB, I3C, PWM, ULPI, Linux, Python.
Work experience
Project Officer II at NG-RAN IIT Hyderabad, Nov 2025 - Present · 11 mos, Hyderabad, Telangana, India
Design Verification Engineer I at SmartSoC Solutions Pvt Ltd, Nov 2024 - Nov 2025 · 1 yr 1 mo, Hyderabad, Telangana, India
Design Verification Engineer I at SmartSoC Solutions Pvt Ltd, Aug 2023 - Oct 2024 · 1 yr 3 mos, Hubli, Karnataka, India
Education
Bachelor of Engineering - BE, Electronics & Communications Engineering, Vasavi College of Engg
Intermediate, MPC, Nano Junior College
