---
title: "RAGHAVAN S U - ASIC Tooling & Verification Contributor (Google PDK Ecosystem) in Bengaluru | Tal"
description: "Meet RAGHAVAN S U, ASIC Design Engineer | RISC-V Architecture | RTL-to-GDSII | Analog Mixed-Signal DV (UVM)| PSG TECH 26’ based in Bengaluru. AI stack includes aistudio, claude code, and n8n. Explore public work links including github and raghavan-04.github.io."
image: "https://tal.club/meet/raghavan-s-u/share-image"
---

# RAGHAVAN S U on Tal

## Headline

ASIC Design Engineer \| RISC\-V Architecture \| RTL\-to\-GDSII \| Analog Mixed\-Signal DV \(UVM\)\| PSG TECH 26’

## About

I am a Silicon Design & Verification Engineer specializing in custom SoC architectures, AI hardware accelerators, and RTL\-to\-GDSII physical design flows\. Recently graduated from PSG College of Technology, my hands\-on portfolio includes timing\-closed RISC\-V processors \(SkyWater 130nm\), 4\-lane SIMD vector datapath architectures, and mixed\-signal DV for Texas Instruments\. I am highly proficient in modern open\-source and industry\-standard EDA tools \(OpenLane, Verilator, Cadence Virtuoso\) and AMBA protocols \(AXI/APB\)\.Actively seeking full\-time roles in ASIC Design, Design Verification \(DV\), or Physical Design\. Tech Stack: SystemVerilog, UVM, C\+\+, Python, Tcl, OpenLane, Sky130/GF180\.

## Location

Bengaluru

## AI stack

aistudio

claude code

n8n

## Work experience

ASIC Tooling & Verification Contributor \(Google PDK Ecosystem\) at FOSSi Foundation, Jun 2026 \- Present · 3 mos, Bengaluru, Karnataka, India

Community Member at RISC\-V International, Mar 2026 \- Present · 6 mos, Remote, • Tracking technical specifications and ISA extensions through the official RISC\-V mentoring and developer channels\. • Engaging with community forums and working groups to align personal RTL design and processor verification practices with industry standards\. • Reviewing open\-source core implementations and architecture design methodologies to support prospective hardware code contributions\.

Open Source Developer at Open Source Initiative \(OSI\), Dec 2025 \- Jun 2026 · 7 mos, Bengaluru, Karnataka, India, Independent hardware developer actively contributing to the open\-source silicon and EDA ecosystem, specializing in digital IC design, computer architecture, and RTL engineering\. Key Open\-Source Projects & Contributions: • Custom RISC\-V Audio SoC \(RV32IM ISA\): Architected a custom 32\-bit single\-cycle processor in SystemVerilog\. Implemented an AMBA AXI4\-Lite Crossbar Router Matrix, an AXI4\-Lite to AMBA APB Bridge subsystem, and a 1KB synchronous Data SRAM\. Completed the entire OpenLane RTL\-to\-GDSII physical ASIC design flow using the SkyWater 130nm PDK\. • Hardware Accelerators: Designed a high\-performance, 2\-stage pipelined Multiply\-Accumulate \(MAC\) Unit, optimizing the critical path for high\-frequency retirement utilizing Fixed\-Point arithmetic\. Technical Frameworks Used: SystemVerilog, Verilog, OpenLane flow, Verilator \(C\+\+ cycle\-accurate simulation\), GTKWave, GitHub Actions, and RISC\-V Assembly firmware\. My Repositories: View my open\-source RTL code, verification testbenches, and hardware architecture layouts directly on my profile: \[https://github\.com/Raghavan\-04/\]

Intern at Minthomes Pvt Ltd, May 2025 \- Jun 2025 · 2 mos, Coimbatore, Tamil Nadu, India, Assisted in IT process management and data analysis during a two\-month internship\. Contributed to team coordination and gained exposure to corporate workflows in an engineering environment\.

## Education

Bachelor of Engineering in Electronics and Communication Engineering, PSG College of Technology

## Public links

- github: https://github\.com/Raghavan\-04
- raghavan\-04\.github\.io: https://raghavan\-04\.github\.io/

[View the original profile](https://tal.club/meet/raghavan-s-u)

```json
{
  "@context": "https://schema.org",
  "@graph": [
    {
      "@type": "Person",
      "@id": "https://tal.club/meet/raghavan-s-u#person",
      "name": "RAGHAVAN S U",
      "url": "https://tal.club/meet/raghavan-s-u",
      "image": "https://tal.club/meet/raghavan-s-u/profile-photo.jpg",
      "description": "Meet RAGHAVAN S U, ASIC Design Engineer | RISC-V Architecture | RTL-to-GDSII | Analog Mixed-Signal DV (UVM)| PSG TECH 26’ based in Bengaluru. AI stack includes aistudio, claude code, and n8n. Explore public work links including github and raghavan-04.github.io.",
      "jobTitle": "ASIC Tooling & Verification Contributor (Google PDK Ecosystem)",
      "worksFor": {
        "@type": "Organization",
        "name": "FOSSi Foundation"
      },
      "hasOccupation": {
        "@type": "Occupation",
        "name": "ASIC Tooling & Verification Contributor (Google PDK Ecosystem)"
      },
      "homeLocation": {
        "@type": "Place",
        "name": "Bengaluru"
      },
      "alumniOf": [
        {
          "@type": "EducationalOrganization",
          "name": "PSG College of Technology"
        }
      ],
      "knowsAbout": [
        "aistudio",
        "claude code",
        "n8n"
      ],
      "sameAs": [
        "https://github.com/Raghavan-04",
        "https://raghavan-04.github.io/"
      ],
      "mainEntityOfPage": {
        "@id": "https://tal.club/meet/raghavan-s-u#webpage"
      }
    },
    {
      "@type": "ProfilePage",
      "@id": "https://tal.club/meet/raghavan-s-u#webpage",
      "url": "https://tal.club/meet/raghavan-s-u",
      "name": "RAGHAVAN S U on Tal",
      "description": "Meet RAGHAVAN S U, ASIC Design Engineer | RISC-V Architecture | RTL-to-GDSII | Analog Mixed-Signal DV (UVM)| PSG TECH 26’ based in Bengaluru. AI stack includes aistudio, claude code, and n8n. Explore public work links including github and raghavan-04.github.io.",
      "dateModified": "2026-08-28T11:30:32.432Z",
      "isPartOf": {
        "@id": "https://tal.club/#website"
      },
      "mainEntity": {
        "@id": "https://tal.club/meet/raghavan-s-u#person"
      },
      "primaryImageOfPage": {
        "@type": "ImageObject",
        "url": "https://tal.club/meet/raghavan-s-u/profile-photo.jpg",
        "contentUrl": "https://tal.club/meet/raghavan-s-u/profile-photo.jpg",
        "caption": "RAGHAVAN S U profile photo on Tal"
      },
      "inLanguage": "en-IN"
    }
  ]
}
```