Headline

Design Verification Engineer at Google

About

Design Verification Engineer, with demonstrated knowledge of SystemVerilog, Verilog, and UVM. Experienced in the functional verification of Memory Caches, Serial and Parallel protocols. Worked on the development of Verification IPs for many protocols such as USB (3.0, 3.1, 3.1 Retimer), DisplayPort (2.0, 1.x), AMBA (AXI, APB, AHB, and AXI4 Stream), TileLink, and MIPI(DSI2). Solely handled verification of a RISC-V Instruction Cache IP. Good knowledge of interconnects/crossbars, Worked on the development of the TileLink crossbar BFM. Developed multi-environment testing scenarios, and enhanced the interconnect scoreboard for Netspeed NoC. Developed a 5 stage pipelined microprocessor based on RISC-V ISA as a college project. My areas of interest are Microprocessors, Interconnects/Crossbars, SoCs and Automation.

Location

Greater Delhi Area

AI stack

antigravity

claude code

claude

gemini

geminicli

notebooklm

Work experience

ASIC Silicon Design Verification Engineer at Google, Aug 2026 - Present · 2 mos, Bangalore Urban

ASIC Engineer, Design Verification at Meta, May 2025 - Aug 2026 · 1 yr 4 mos, Bangalore Urban, At Meta, I focus on the design verification of debug subsystems that support AI inference and data center chip functionalities. My role involves collaborating with cross functional teams to streamline verification processes and enhance system reliability.

Lead Member Technical Staff at Siemens EDA (Siemens Digital Industries Software), Jan 2023 - May 2025 · 2 yrs 5 mos, Noida, Uttar Pradesh, India

Senior Member Technical Staff at Siemens EDA (Siemens Digital Industries Software), Apr 2021 - Jan 2023 · 1 yr 10 mos, Noida, Uttar Pradesh, India, DisplayPort 2.0 -- Coded all the enhancements for the Source and Sink BFM. -- Enhanced the Link Training code to handle fallbacks of speed. -- Added support for Re-timer training via the AUX commands. -- Added new tests to verify the functionality. DisplayPort 1.x -- Enhancements for FEC and bug fixes.

Design Engineer at Truechip Solutions, Feb 2020 - Apr 2021 · 1 yr 3 mos, Noida Area, India, Instruction Cache Verification -- Developed a full verification environment for the Cache verification from scratch. -- Developed a golden model BFM of cache. -- Developed cache monitors and cache scoreboards. -- Functionally verified the Instruction Cache using the developed environment. -- Created a robust test plan to cover corner cases. -- Found multiple bugs in RTL. -- Achieved 100% code and functional coverage. TileLink -- Writing slave BFM from scratch. -- Foundational development of Crossbar BFM. -- Development of Testplan for complex caching scenarios for TL-C. -- Writing tests and sequences for TL-C. AXI3/4/4Lite/5/5Lite: -- Enhancements for AXI5 Atomic and trace signals. -- Functional testing. -- Interconnect testing. -- Bug Fixing and Enhancements. -- User support. AXI4STREAM: -- Writing scoreboard from scratch. -- Making test plan and coverage plan -- Writing tests and Sequences. MIPI DSI2 -- Adding enhancement for DSI2 in the reception side of LM and LLP layers. -- Adding support for C-PHY. -- Writing test cases and sequences. AHB -- Enhancing RAL adaptor. -- Adding new tests for RAL.

Design Engineer Trainee at Truechip Solutions, May 2019 - Feb 2020 · 10 mos, Noida Area, India, Worked on USB 3.x Link Layer, PHY layer, and Re-timers. BFM enhancement. Bug fixing. Testbench integration and setup support.

Design Intern at 3ST Technologies, Jan 2019 - Apr 2019 · 4 mos, Noida Area, India

Education

Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering, Manav Rachna University

Science (PCM), DAV Public School, Sector 14, Gurgaon