Headline

Senior Software Engineer @ Mirafra -​>Google | l Ex- Digicomm l | Ex- Harman | Ex-Tessolve -​> Intel

About

With a Master of Technology degree from GITAM University in Power System Automation, I most recently served as a Lead Engineer at Digicomm Semiconductor. My work focused on leading validation efforts for next-generation SoC platforms, with particular emphasis on PCIe and CXL subsystem IPs. Core strengths include pre-silicon and post-silicon validation strategies, test plan authoring, and collaborating with design and firmware teams to ensure comprehensive feature coverage. Past experiences at HARMAN International and Tessolve deepened my expertise in PCIe and CXL validation, Python scripting for automated testing, and advanced debugging techniques using tools like Protocol Analyzers and JTAG/TRACE32. I am driven to contribute to innovative solutions, working alongside cross-functional teams to achieve shared goals. My ability to mentor peers and streamline validation processes ensures high-quality outcomes aligned with organizational objectives.

Location

India

AI stack

gemini

Work experience

Senior Software Engineer at Mirafra Technologies, Jul 2026 - Present · 3 mos, Bangalore Urban

Lead Engineer at Digicomm Semiconductor, Feb 2026 - Apr 2026 · 3 mos, Bangalore Urban, Leading validation efforts on next-generation SoC platforms with focus on PCIe and CXL subsystem IPs. Driving pre-silicon and post-silicon validation strategies, test plan authoring, and feature coverage. Collaborating with design and firmware teams to define and execute comprehensive validation scope.

Lead Product Engineer at HARMAN International, Nov 2024 - Feb 2026 · 1 yr 4 mos, Bangalore Urban, Spearheaded PCIe Gen5/4/3/2 and CXL post-silicon validation activities for SoC platforms. Led test planning, feature coverage, and protocol compliance validation across multiple IPs. Utilized SAGE, Tool-Stream, Ubisoft, and DTT UI tools for advanced validation workflows. Mentored junior engineers in PCIe/CXL testing methodology and lab equipment operation.

Sr.System Validation Engineer at Tessolve, Jul 2023 - Jul 2024 · 1 yr 1 mo, Bengaluru, Executed 200+ test cases for PCIe Gen5/4/3 endpoints and root complex validation. Programmed and brought up CXL cards; executed compliance and functional validation using MXL tool, cxlcv.app, and CScripts. Developed Python test suites from scratch for PCIe Gen5/4/3 and CXL compliance achieving full-feature validation. Automated test environments in C and Python for Linux systems; validated & monitored link training. Resolved data transmission and retrain failures at HW/SW interface; managed bug tracking via Jira. Performed board bring-up, schematic analysis, and root cause identification using (T516)Protocol Analyzers (Beagle, Total Phase), DSOs, JTAG/TRACE32, and DMM.

System Validation Engineer at Tessolve, Sep 2021 - Jul 2023 · 1 yr 11 mos, Bangalore Urban, Conducted power-on validation, board-level debug, and schematic analysis for embedded SoC platforms. Executed NVMe controller validation: initialization flow, shutdown flow, register mapping, and functional feature testing. Developed content for NVMe system-level test plan; collaborated with designer teams for feature coverage. Analyzed signal traces and IP register dumps; performed in-depth diagnostics with Beagle total phase (I2C/SPI JTAG)logical Analyzers. Developed BDF-based traffic generation and PF/VF configuration strategies for scalable validation coverage.

Intern at ISRO - Indian Space Research Organization, Feb 2018 - Jan 2019 · 1 yr, Gujarat, India, I have hands-on experience in the design, development, testing, and validation of high-reliability electronic hardware used in demanding industrial and defense-oriented environments. My work has focused on developing robust electronic systems that meet stringent quality, performance, and reliability requirements. I have practical knowledge of working with military-grade electronic equipment, where reliability, environmental tolerance, and long-term performance are critical. My responsibilities have included hardware bring-up, subsystem integration, functional verification, troubleshooting, and validation of electronic assemblies using laboratory instruments such as oscilloscopes, logic analyzers, spectrum analyzers, digital multimeters, programmable power supplies, and signal generators. My experience in magnetic component design includes the design and optimization of inductors for DC-DC converters, EMI filtering, and power management applications. I have worked on selecting suitable core materials, calculating inductance values, determining wire gauge, estimating current carrying capacity, minimizing core losses, and evaluating thermal performance. I have also pe

Education

Power system Automation, Gandhi Institute of Technology and Management (GITAM)

EEE, JNTU Anantapur

Public links

github: https://github.com/ragava1103