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preethi katipally

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Hyderabad

Work experience

Designer and Analysis of Low Power High Speed Full Adder Cell
- NowPresent

In this project, the circuit level optimization process is followed to reduce the area and power. In the conventional technique, complementary static CMOS (CSCMOS) technology is used to design a parallel self-timed adder circuit, in which the number of NMOS and PMOS are equal. Also, large number of transistors are required to design any logic gate or digital circuits. To overcome this problem, the modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self-time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. Integration of Optimized GDI Logic based XOR Gate and Half Adder into PASTA for Low Power and Area.

Education

B.Tech (E.C.E)

Balaji institute of technology and science

20194 yrs2023

Intermediate (M.P.C)

Sr.junior college

20162 yrs2018

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Headline

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About

A highly motivated and passionate graduate seeking entry-level opportunities in Embedded Systems and/or Robotics. Eager to learn and contribute to innovative projects, with academic experience in working with micro-controllers. Strong understanding of embedded software design. Proficient in C, C++, Arduino-based software development.

Location

Hyderabad

Work experience

Project Work at Designer and Analysis of Low Power High Speed Full Adder Cell, In this project, the circuit level optimization process is followed to reduce the area and power. In the conventional technique, complementary static CMOS (CSCMOS) technology is used to design a parallel self-timed adder circuit, in which the number of NMOS and PMOS are equal. Also, large number of transistors are required to design any logic gate or digital circuits. To overcome this problem, the modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self-time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. Integration of Optimized GDI Logic based XOR Gate and Half Adder into PASTA for Low Power and Area.

Education

B.Tech (E.C.E), Balaji institute of technology and science

Intermediate (M.P.C), Sr.junior college

preethi katipally - Project Work in Hyderabad | Tal