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Pranjal Jagwani

Student at Vellore Institute of Technology - EEE '25 | UI/UX Enthusiast

Chennai

< 1 year of work experience

Maven Silicon
Aug 20233 mosOct 2023

Bengaluru, Karnataka, India

Worked and received training as a VLSI Design Intern, who worked on a SPI Design Project.
Maven Silicon
Aug 20233 mosOct 2023

Led hands-on VLSI design flows through an SPI Design Project. Successfully verified RTL design functionality by simulating waveforms for Clock Generator, Shift Register, and the complete SPI Master Core (MISO, MOSI, and Top Module), ensuring robust serial communication.

Pranjal’s AI Stack

kiro
kiro
langsmith
langsmith
openclaw
openclaw
perplexity
perplexity

Education

Vellore Institute of Technology

Bachelor of Technology - BTech, Electrical and Electronics Engineering

Vellore Institute of Technology

20214 yrs2025

Higher Secondary School (12th Grade), Science

BASE, Bannerghatta Road, Bengaluru

20192 yrs2021

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Headline

Student at Vellore Institute of Technology - EEE '25 | UI/UX Enthusiast

About

As an enthusiastic and aspirational student at Vellore Institute of Technology in Chennai, I am committed to academic achievement and am driven by a great curiosity. I am pursuing a Bachelor of Technology in Electronics and Electrical Engineering. My drive to learn new things and be innovative drives my engineering path and grasping challenging topics in my area. Aside from academics, I have a strong interest in art and culture, which inspires original thought and helps me approach issues from a different angle. My ability to contribute to initiatives that call for both analytical thinking and creative solutions stems from my combination of technical skill and artistic interest. Presently, I'm committed to honing my UI and UX design abilities and broadening my knowledge of the fundamentals of electrical and electronic engineering. I am eager to take advantage of the chances that lie ahead and contribute significantly to the field of technology.

Location

Chennai

AI stack

kiro

langsmith

openclaw

perplexity

Work experience

VLSI Design Intern at Maven Silicon, Aug 2023 - Oct 2023 · 3 mos, Bengaluru, Karnataka, India, Worked and received training as a VLSI Design Intern, who worked on a SPI Design Project.

Design Internship at Maven Silicon, Aug 2023 - Oct 2023 · 3 mos, Led hands-on VLSI design flows through an SPI Design Project. Successfully verified RTL design functionality by simulating waveforms for Clock Generator, Shift Register, and the complete SPI Master Core (MISO, MOSI, and Top Module), ensuring robust serial communication.

Education

Bachelor of Technology - BTech, Electrical and Electronics Engineering, Vellore Institute of Technology

Higher Secondary School (12th Grade), Science, BASE, Bannerghatta Road, Bengaluru

Pranjal Jagwani - VLSI Design Intern in Chennai | Tal