Headline

Verification Engineer | Former Intern at Synopsys | SystemVerilog & UVM | ASIC Verification | RTL Verification | VLSI Engineer

About

Verification Engineer with 1 year of internship experience at Synopsys in the DDR PHY team. Experienced in SystemVerilog, UVM, RTL Verification, and debugging complex verification environments related to high-speed memory interfaces. Strong understanding of ASIC verification methodologies, constrained random verification, assertions, and protocol-based verification. Familiar with industry-standard protocols and verification flows. Passionate about solving complex design challenges and building reusable verification environments.

Location

Chinaganjam

Work experience

Intern at Synopsys Inc, May 2025 - May 2026 · 1 yr 1 mo, Bengaluru, Karnataka, India, Executed and managed regression testcases, improving regression pass rate to ~98% through systematic debugging and issue resolution. Debugged testbench and design-level failures, accelerating bug triage and reducing turnaround time for regression closure. Improved code coverage from 89% to 99%, by enhancing stimulus, refining test scenarios, and closing coverage holes. Debugged and enhanced checkers and validation logic, improving verification robustness and early bug detection. Created Nested IP (NIP) versions for regression environments, enabling customer-specific configuration of IP builds across multiple CLs. Performed protocol-level verification for DDR5/DDR4 PHY and controller, ensuring compliance with timing and functional requirements. Collaborated with cross-functional teams to debug issues and improve the verification environment stability.

Trainee at Maven Silicon, Jul 2024 - Apr 2025 · 10 mos, Bengaluru, Karnataka, India, Advanced ASIC verification trainee

Education

Master of Technology - MTech, VLSI, Amrita School of Engineering, Bangalore

Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, Jobs in Tamil Nadu India