Headline

Technical Lead at Quest Global

About

I have 9.2 years of expertise in Analog and Digital IC layout design, complemented by industry-level training from RV-VLSI. My experience spans leading projects for prominent clients like Intel, Qualcomm, and Bosch, working across diverse nodes and technologies including Intel 7nm & 5nm and TSMC 3nm. Noteworthy achievements include managing teams to deliver critical blocks from scratch, such as LDOs and DACs, and efficiently handling ESD circuits and DFM checks. Proficient in tools like Cadence Virtuoso and Calibre, I excel in PV, DFM, and RV checks, ensuring top-notch quality. I hold a Bachelor's in Electronics and Communication Engineering. I am eager to bring my proven track record of excellence and collaborative approach to drive success in IC layout design.

Location

Chennai

AI stack

antigravity

codex

cursor

Work experience

Technical Lead at Quest Global, Aug 2024 - Present · 2 yrs 1 mo, Bengaluru, Karnataka, India

Senior Layout Engineer at Capgemini Engineering, Feb 2019 - May 2025 · 6 yrs 4 mos, Malaysia

Layout Engineer at UST Global, Aug 2017 - Dec 2018 · 1 yr 5 mos, Malaysia

Layout Design Engineer at Cyient, Jun 2015 - Jul 2017 · 2 yrs 2 mos, Hyderabad, Telangana, India, Worked on the Floorplannig,Routing & Verfication in modules such as Pipelined ADC, PLL ,Voltage sensors, Adaptive clock Distribution system.Had hands on experience on lower technology nodes such as 10nm & 14nm.

Education

Bachelor’s Degree, Electrical, Electronics and Communications Engineering, Jeppiaar SRR Engineering college

High School, Computer Science, Vidyaa vikas matriculation higher sceondary school