Headline

Senior Staff / Principal Engineer | System Software & CPU Performance | Embedded & SoC | Video & Audio Codecs | Automotive | DSP | C/C++ | Linux | ARM NEON & AVX2 | AI/ML

About

I am a Senior Staff / Principal-level engineering professional with 22+ years of experience building and optimizing performance-critical software across CPUs, DSPs and heterogeneous SoCs. My experience spans system software, embedded systems, video and audio codecs, automotive platforms, DSP/SIMD optimization and AI/ML, with engineering roles across Intel, Harman, Western Digital/SanDisk, Cisco, Aricent and Tata Elxsi. My core strength is working at the hardware-software boundary—understanding workloads, identifying architectural and performance bottlenecks, and translating those insights into efficient software implementations. I have worked across ARM, x86 and multiple DSP architectures, optimizing compute-intensive algorithms using C/C++, assembly, SIMD/intrinsics, ARM NEON and Intel AVX2. Over the course of my career, I have designed, developed and optimized video and audio codec technologies including AV1, HEVC/H.265, H.264/AVC, VC-1, MPEG-4, EAAC+ and iLBC. My work has included codec architecture, encoder/decoder development, real-time optimization and performance-critical multimedia libraries across embedded and high-performance platforms. I have also worked extensively on automotive and embedded systems, including ADAS-related platforms, Driver Monitoring Systems (DMS), camera/video systems and heterogeneous automotive SoCs. This experience spans system architecture, hardware-software integration, real-time processing, performance analysis and optimization. More recently, I have applied AI/ML techniques to video and system optimization problems, including ML-based encoder/decoder technologies, video super-resolution, motion-aware temporal processing and CNN-based approaches. Key areas of expertise: • System software and CPU performance optimization • Embedded systems and heterogeneous SoC architecture • C/C++, assembly, SIMD, ARM NEON and Intel AVX2 • DSP architecture and performance optimization • Video and audio codec architecture and optimization • Linux, Android and Chrome OS • Performance profiling, benchmarking and workload analysis • Automotive, DMS, camera and real-time video systems • AI/ML and computer vision for multimedia and system optimization I enjoy solving engineering problems where architecture, algorithms, software and hardware performance intersect—particularly problems requiring deep analysis, optimization and system-level design.

Location

Greater Bengaluru Area

AI stack

openai

Work experience

Software Engineer at Intel Technologies Pvt. Ltd, 2022 - Present · 4 yrs 10 mos, • Spearhead architecture and delivery for a three-engineer ASTC texture-compression project; secured invention approval, completed chipset porting and advanced patent filing. • Pioneer Motion Loss and Codec-Aligned Motion Loss techniques for CNN-based video super-resolution, achieving 27.96 dB PSNR and 0.843 SSIM on 2x super-resolution while enforcing temporal motion consistency, securing invention disclosure approval at Intel. • Accelerated an FFT workload by 18% using Intel AVX2 optimization, validated with Android performance profiling. • Characterize compute-intensive codec and rate-control workloads using benchmarks and profiling to isolate kernel, memory and system bottlenecks. • Engineer Chrome OS and Android media components across AV1, AOM, libva-utils, Intel multimedia libraries and asynchronous video-processing pipelines. • Drive Linux and Chrome OS protected-content integration, including DRM, protected-buffer management and user-space media handling. • Develop a CNN-based video super-resolution proof of concept and assess integration into performance-critical multimedia pipelines; selected for the Agentic AI VSR internal demonstration at Intel TID 2026. • Produce architecture specifications and technical white papers for rate control, multimedia systems and performance optimization.

System Software Engineer at Intel Corporation, Mar 2022 - Sep 2026 · 4 yrs 7 mos, Bengaluru, Karnataka, India, Android Media side, Video codecs, Applying CNN models to Video domain. Proposed invention on ASTC, and Motion loss to be used on video super resolution Received internal invention approval for a novel ASTC (Adaptive Scalable Texture Compression) technique; led a 3-engineer team to port it to Intel's latest chipset. Filing in progress. Optimize FFT routines on Intel AVX2, achieving an 18% performance gain, measured on Android OS using simpleperf. Built and demoed a video super-resolution model using only 0.5M parameters; filed an invention disclosure on Motion Loss. Lead the FFmpeg/GStreamer team contributing to the Chrome OS/ALOS media stack, focused on video codec optimization and rate control. Enabled rate control for video codecs including AV1 through contributions to libmebo, libva-utils, and the AOM open-source project. Received the Intel GAR Award for AV1 codec rate-control modifications on the MTL platform. Authored and presented an internal white paper on rate-control architecture and improvements. Developing a CNN-based proof of concept to enhance video resolution for potential productization. Awarded Quarterly Bonus multiple times for contributions to codec performance and exploration initiatives.

Senior Principal Engineer at HARMAN International, Apr 2021 - Apr 2022 · 1 yr 1 mo, Led a 4-member team to demonstrate a Camera Mirror System (CMS) for automotive applications, designing the software architecture to replace physical mirrors with camera-based video feeds. Integrated OpenVX for real-time video processing and OpenCV for camera interfacing; used Qualcomm reference code and ensured multithreaded performance across the pipeline. Received positive management feedback for effective team leadership and delivery. Contributed to Driver Monitoring System (DMS) enablement on Samsung SoCs, including requirement analysis, code repository ownership, and architecture documentation. Collaborated with cross-functional teams and customers to finalize CMS features and system design, and evaluated computer vision algorithms (lane detection, object detection) for platform suitability.

SW Architect--ADAS systems at HARMAN International, Feb 2021 - May 2022 · 1 yr 4 mos, Bengaluru, Karnataka, India, Worked as a Software Architect on automotive ADAS and in-cabin vision systems, focusing on embedded system architecture, real-time video processing, camera pipelines and hardware-software integration. • Architected and developed Driver Monitoring System (DMS) and camera-based automotive solutions on heterogeneous SoC platforms. • Worked with NXP i.MX8X and Renesas R-Car H3 platforms, integrating and optimizing software across CPU, accelerator and embedded processing environments. • Designed software architecture and data flows for real-time camera/video processing, with emphasis on system performance, latency, resource utilization and reliability. • Worked across embedded Linux, device/platform software, multimedia frameworks and hardware interfaces to enable end-to-end automotive functionality. • Collaborated across hardware, software, algorithm and system teams to analyze performance bottlenecks, resolve integration issues and optimize system behavior. • Applied extensive multimedia, DSP and system-level optimization experience to automotive vision and ADAS workloads.

Senior Technical Lead at PathPartner Technologies, Apr 2019 - Mar 2021 · 2 yrs, Bengaluru, Karnataka, India, Led architecture and development of automotive Driver Monitoring System (DMS) solutions across heterogeneous SoC platforms, combining ARM, DSP, MCU and ML accelerators for real-time in-cabin intelligence. • Led a 4-engineer team for DMS enablement on Broadcom BCM89107 (8 DSP cores + ARM), owning software architecture, workload scheduling, task management, inter-core communication and synchronization. • Enabled ML-based DMS algorithms on BCM89107, architecting the software and execution model to meet embedded automotive platform requirements. • Led DMS enablement on the Qualcomm Snapdragon 8155 automotive platform while overseeing two additional DMS programs in parallel. • Architected a DMS solution using CEVA DSP + MCU, enabling neural-network inference directly on the DSP and integrating the processing pipeline within embedded system constraints. • Delivered DMS solutions across multiple heterogeneous compute architectures, including ARM-based and DSP/MCU-based platforms, adapting software architecture, workload partitioning and execution models to different hardware capabilities. • Provided technical leadership across architecture, platform bring-up, integration, performance analysis and issue resolution, working across algorithm, platform and embedded software teams.

Staff Firmware Engineer at SanDisk, a Western Digital Brand, Nov 2016 - Mar 2019 · 2 yrs 5 mos, Bengaluru, Karnataka, India, Principal Engineer in client SSD firmware development, working on flash-storage architecture, ASIC bring-up and firmware development for next-generation 3D NAND and cost-optimized SSD controller platforms. • Contributed to client SSD firmware development and platform enablement for new 3D NAND technologies and low-cost ASICs targeting the client compute market. • Designed firmware modules for the physical storage layer of flash controllers, including algorithms related to flash management, data handling and NAND operations. • Developed and enhanced algorithms across FLGP, RS, RLC and 2CH components, including architecture/design documentation (HLD/LLD), implementation, debugging and integration. • Supported ASIC bring-up from the firmware side, identifying firmware dependencies and feature requirements and coordinating integration across ASIC, IP, memory, simulation, validation and software-tools teams. • Worked on firmware profiling, performance analysis, feature enhancement and complex defect resolution in collaboration with validation and platform teams. • Contributed to SSD reliability and data-protection mechanisms, including XOR-based recovery, data relocation and read-scrubbing algorithms. • Participated in architecture/design reviews, code reviews, unit-test framework analysis and system-level integration and validation. • Served as Scrum Master for firmware activities during ASIC bring-up, driving sprint planning, technical dependency tracking and execution across cross-functional engineering teams while providing status visibility to senior management.

Education

Master's degree, Data scince and Machine laearning, P.E.S

BE, ELECTRONICS AND COMMUNICATIONS, NATIONAL INSTITUTE OF ENGINEERING.MYS.