Piyush Yenkar profile photo 1 on Tal

Piyush Yenkar

Digital Design Engineer

Bengaluru

9+ years of work experience

Synopsys Inc
Feb 20242 yrs 8 mosPresent

Banglore

ATE simulations , ATE Silicon validation, sequence delivery ,PDL Generation, Customer Silicon Bringup support on ATPG pattern debug , ARE functional failures (9 projects)
Synopsys Inc
Mar 20231 yrFeb 2024

Bengaluru, Karnataka, India

DFT ,Scan insertion ,ATPG, Pattern Simulation , ATE for SERDES IP, Packaging, Synthesis
Intel Corporation
Dec 20211 yr 4 mosMar 2023

Greater Bengaluru Area

Intel Corporation
Mar 20211 yr 1 moMar 2022

Bengaluru, Karnataka, India

Graphics (GPU) — Scan / DFT Debug • Developed scan chain analysis tools on GPU DFT infrastructure for faster debug of on-chip scan data • Partnered with design teams on DFT collateral to meet debug and diagnosis tool requirements • Worked with PSV team to analyze on-chip scan dump data and correlated failures to design blocks and scan segments • Validated security and RAS features via fault-injection pass/fail scenarios and intentional error injection • Supported scan-based debug workflows used during GPU validation and silicon bring-up activities.
MediaTek
Jul 20209 mosMar 2021

Bengaluru, KA, India

MediaTek
May 202011 mosMar 2021

Mobile Core Processors • Generated ATPG patterns for stuck-at and transition fault models using TetraMAX. Creating basic and fast sequential patterns to meet coverage and runtime targets. • Performed scan insertion by defining constraints and multiple scan configurations at block level. • Ran scan DRC checks and resolved controllability/observability and clocking issues before pattern generation. • Ported, merged, and verified patterns at sub-block, block, and chip levels. • Supported compression and scan chain integration for mobile processor DFT signoff.
onsemi
Oct 20172 yrs 8 mosMay 2020

CMOS Image Sensor (Automotive) • Debugged production SCAN and MBIST failures with DFT team using Tessent Silicon Insight and YieldInsight RCD. • Performed bench validation, characterization, and yield analysis. Driving yield improvement at PVT corners. • Brought up and optimized test programs. Correlating bench vs tester results and defining probe test limits. • Supported automotive reliability testing, product qualification, and package qualification activities. • Proposed hardware fixes at tester for functional issues found at PVT corners and reduced manufacturing cost through tester software and hardware optimizations.
Oct 20171 yr 1 moOct 2018

Banglore

Piyush’s AI Stack

claude
claude

Education

Vellore Institute of Technology

Master's degree, Electrical and Electronics Engineering

Vellore Institute of Technology

20152 yrs2017

Bachelor's degree, Electrical and Electronics Engineering

P.D.V.V.P.COE,Ahmednagar

20094 yrs2013

Join Piyush and 10k+ other professionals on

Tal Boss

Tal is the app where bosses meet engineers & builders directly, without middlemen

Download Tal Boss

Piyush Yenkar on Tal

Headline

Digital Design Engineer

About

Synopsys (Serdes) DFT,Packiging, ATE Simulations, Automations, multiple silicon bringups Graphics Design (GPU) Methodology and DFX Tool lead Sr DFT Engineer at Mediatek, Banglore Mobile Market (5G) DFT Scan pattern geneation and simulation for mobile chips [3nm] Post Silicon Validation & Test Engineer ONSemiconductor, Banglore CMOS Image Sensors MBIST Validation , Product post silicon validation and ATE yeild analysis/improvemnet

Location

Bengaluru

AI stack

claude

Work experience

Staff Engineer at Synopsys Inc, Feb 2024 - Present · 2 yrs 8 mos, Banglore, ATE simulations , ATE Silicon validation, sequence delivery ,PDL Generation, Customer Silicon Bringup support on ATPG pattern debug , ARE functional failures (9 projects)

Sr Digital Design Engineer at Synopsys Inc, Mar 2023 - Feb 2024 · 1 yr, Bengaluru, Karnataka, India, DFT ,Scan insertion ,ATPG, Pattern Simulation , ATE for SERDES IP, Packaging, Synthesis

Graphics Hardware Engineer at Intel Corporation, Dec 2021 - Mar 2023 · 1 yr 4 mos, Greater Bengaluru Area

System Validation Engineer at Intel Corporation, Mar 2021 - Mar 2022 · 1 yr 1 mo, Bengaluru, Karnataka, India, Graphics (GPU) — Scan / DFT Debug • Developed scan chain analysis tools on GPU DFT infrastructure for faster debug of on-chip scan data • Partnered with design teams on DFT collateral to meet debug and diagnosis tool requirements • Worked with PSV team to analyze on-chip scan dump data and correlated failures to design blocks and scan segments • Validated security and RAS features via fault-injection pass/fail scenarios and intentional error injection • Supported scan-based debug workflows used during GPU validation and silicon bring-up activities.

Senior DFT Engineer at MediaTek, Jul 2020 - Mar 2021 · 9 mos, Bengaluru, KA, India

Senior Test Engineer at MediaTek, May 2020 - Mar 2021 · 11 mos, Mobile Core Processors • Generated ATPG patterns for stuck-at and transition fault models using TetraMAX. Creating basic and fast sequential patterns to meet coverage and runtime targets. • Performed scan insertion by defining constraints and multiple scan configurations at block level. • Ran scan DRC checks and resolved controllability/observability and clocking issues before pattern generation. • Ported, merged, and verified patterns at sub-block, block, and chip levels. • Supported compression and scan chain integration for mobile processor DFT signoff.

Product Test Engineer at onsemi, Oct 2017 - May 2020 · 2 yrs 8 mos, CMOS Image Sensor (Automotive) • Debugged production SCAN and MBIST failures with DFT team using Tessent Silicon Insight and YieldInsight RCD. • Performed bench validation, characterization, and yield analysis. Driving yield improvement at PVT corners. • Brought up and optimized test programs. Correlating bench vs tester results and defining probe test limits. • Supported automotive reliability testing, product qualification, and package qualification activities. • Proposed hardware fixes at tester for functional issues found at PVT corners and reduced manufacturing cost through tester software and hardware optimizations.

Product Engineer ( Intern) at ON SEMICONDUCTOR TECHNOLOGY INDIA PRIVATE LIMITED, Oct 2017 - Oct 2018 · 1 yr 1 mo, Banglore

Education

Master's degree, Electrical and Electronics Engineering, Vellore Institute of Technology

Bachelor's degree, Electrical and Electronics Engineering, P.D.V.V.P.COE,Ahmednagar