---
title: "Pavel Kabiraj - Senior Engineer - GPU Subsystems in Bengaluru | Tal"
description: "Meet Pavel Kabiraj, ● Senior RTL Designer at Qualcomm ● Automotive GPU Subsystems ● Ex @TI, Micron based in Bengaluru. AI stack includes antigravity, claude code, and codex."
image: "https://tal.club/meet/pavel-kabiraj/share-image"
---

# Pavel Kabiraj on Tal

## Headline

● Senior RTL Designer at Qualcomm ● Automotive GPU Subsystems ● Ex @TI, Micron

## About

I design ASIC microarchitectures for compute and memory subsystems \- where correctness, timing closure, and power efficiency are constraints, not afterthoughts\. At Qualcomm, my work is in Automotive GPU subsystem RTL under ISO 26262 \- the memory protection and interrupt control fabric that underpins GPU compute correctness\. ECC architecture, FuSa scheduling logic, and async data transfer across multi\-clock domains, built CDC\-safe and timing\-convergent for automotive\-grade silicon\. At Micron, I owned Server PMIC microarchitecture from spec to silicon \- pipelining timing\-critical datapaths, closing CDC violations across Fast\-to\-Slow and discontinuous clock boundaries, and executing spare\-gate ECOs under tapeout pressure that kept silicon on schedule\. ECO closure ran through full Conformal LEC verification\. At Texas Instruments, my work spanned PLL, SDM, and oscillator systems across multiple silicon cycles \- fractional dividers, phase sync logic, FSM control logic with analog feedback and clean reset sequencing, built for reliability under tight constraints\. The through\-line: RTL that meets PPA targets, closes timing, crosses clock domains cleanly, and survives silicon\. I work closely with DV and backend to ensure my RTL is simulation\-stable, coverage\-aware, and signoff\-ready\. 9 tapeouts\. ASIC RTL, GPU subsystems, mixed\-signal control logic\.

## Location

Bengaluru

## AI stack

antigravity

claude code

codex

cursor

gemini

openai

## Work experience

Senior Engineer \- GPU Subsystems at Qualcomm, Dec 2025 \- Present · 10 mos, Bengaluru, Karnataka, India

Senior Engineer \- Digital Design at Micron Technology, Dec 2024 \- Nov 2025 · 1 yr, Bengaluru, Karnataka, India

Digital Design Engineer at Texas Instruments, Jul 2022 \- Nov 2024 · 2 yrs 5 mos, Bengaluru, Karnataka, India

Digital Design Intern at Texas Instruments, Jun 2021 \- Jul 2021 · 2 mos

## Education

BE \- Bachelor of Engineering, Electronics and Telecommunication Engineering, Jadavpur University, Kolkata

AISSCE \(CBSE\), Arambagh Vivekananda Academy

[View the original profile](https://tal.club/meet/pavel-kabiraj)

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