---
title: "Parth Rastogi - Associate Software Engineer in Greater Delhi Area | Tal"
description: "Meet Parth Rastogi, SWE @ Qualcomm | AIR 3 @ Amazon ML Challenge 2025 | Prev Intern @ST Microelectronics, Laika AI, Infradock AI, Heydo Tech based in Greater Delhi Area. AI stack includes anthropic apis, antigravity, and claude code."
image: "https://tal.club/meet/parth-rastogi-1/share-image"
---

# Parth Rastogi on Tal

## Headline

SWE @ Qualcomm \| AIR 3 @ Amazon ML Challenge 2025 \| Prev Intern @ST Microelectronics, Laika AI, Infradock AI, Heydo Tech

## About

Final\-year CSE student at IIIT Delhi \(Dean's List 2023–26\) specializing in Machine Learning, LLMs, and systems\-level AI\. AIR 3 at Amazon ML Challenge 2025 among 20,000\+ teams\. Meta PyTorch OpenEnv Hackathon Finalist\. Currently building KV cache optimization for VLMs at STMicroelectronics\. Prior to that, 3x startup intern ; building document intelligence pipelines at InfraDock AI, agentic backend systems at Laika AI, and ML sales forecasting at Heydo Tech\. Also hold research experience through IIIT Delhi's CDNM lab and a published arXiv collaboration with Czech Technical University \. Core competencies: Python · PyTorch · LLMs · RAG · FastAPI · AWS · Quantization · Fine\-tuning \(LoRA, QLoRA\) · GPU Programming · Computer Vision · Multimodal ML Open to: SDE / ML Engineer / AI Engineer / Data Scientist/ Research roles — India · USA · Europe · Australia · Remote Let's connect\.\.\.\.

## Location

Greater Delhi Area

## AI stack

anthropic apis

antigravity

claude code

claude

codex

github copilot

## Work experience

Associate Software Engineer at Qualcomm, Jul 2026 \- Present · 3 mos, Hyderabad

Machine Learning Engineer at STMicroelectronics, Feb 2026 \- Jul 2026 · 5 mo, Noida, Authored QUARTZ \(published at COLM 2026\), a novel method that reduces LLM KV\-cache read\-path memory bandwidth by 7\.4x\. Designed calibration\-free analytical codebooks and integer lookup\-based attention to bypass key vector reconstruction entirely\. Achieved 100% passkey retrieval and outperformed FP16 baselines \(0\.88 vs 0\.86\) on a long\-context suite, validating architectural gains using gem5 simulations on ARM Cortex\.

Undergraduate Researcher at Center for Design and New Media \(CDNM\), IIIT\-Delhi, Jan 2026 \- Jul 2026 · 7 mos, Delhi, India, My work builds on a formally defined Interaction Grammar, which treats human robot interaction as a structured, timed contract over observable events\. The work involves Building a schema validator and AST based validation for correctness of contract as per grammar and also a Ros bag validator for validating events against the contract\. Also worked on LLM based report generation and chat interface for the user experience\.

AI Engineer at InfraDock AI, Jan 2026 \- Apr 2026 · 4 mos, Noida, Currently working on building a robust document\-intelligence pipeline to enable automated understanding of large\-scale documents\. My work focuses on: • Designing OCR\-first pipelines to reliably parse scanned PDFs and Word documents • Structuring documents into machine\-readable representations to support downstream LLM\-based reasoning and retrieval

Undergraduate Researcher at Infosys Centre for Artificial Intelligence IIITD, Aug 2025 \- Dec 2025 · 5 mos, Delhi, India, working on Synthetic data generation for creation of an generalized code dataset\.

## Education

Bachelor of Technology \- BTech, Computer Science and Engineering, Indraprastha Institute of Information Technology, Delhi

12th, Science , non medical, St Wilfred's School, panvel

[View the original profile](https://tal.club/meet/parth-rastogi-1)

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