Parna Lata Chaurasia profile photo 1 on Tal

Parna Lata Chaurasia

Final Year Electrical Engineering Student at IIT Bhilai | Embedded & Digital Systems Developer | Control Systems | FPGA Architecture | Verilog & RTL Design

Bhilai

< 1 year of work experience

IISER Bhopal
May 20253 mosJul 2025

The Pixel Snappers
20241 yr2025

ELECTROMOS Sci-Tech Club ,IIT Bhilai
20241 yr2025

Parna’s AI Stack

antigravity
antigravity
codex
codex
cursor
cursor

Education

Indian Institute of Technology, Bhilai

Bachelor of Technology

Indian Institute of Technology, Bhilai

20234 yrs2027
Good Shepherd Convent, Shahdol

12th

Good Shepherd Convent, Shahdol

20211 yr2022

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Headline

Final Year Electrical Engineering Student at IIT Bhilai | Embedded & Digital Systems Developer | Control Systems | FPGA Architecture | Verilog & RTL Design

About

Currently pursuing a Bachelor of Technology at the Indian Institute of Technology, Bhilai, with an expected graduation in 2027. Educational focus emphasizes electrical engineering, supported by competencies in Cadence Virtuoso, power electronics, and C programming. Completed a Summer Research Internship at IISER Bhopal, gaining hands-on exposure to practical applications in engineering. Committed to developing expertise in embedded systems and digital technologies while contributing to innovative solutions in electronic system development.

Location

Bhilai

AI stack

antigravity

codex

cursor

Work experience

Summer Research Intern at IISER Bhopal, May 2025 - Jul 2025 · 3 mos

Member at The Pixel Snappers, 2024 - 2025 · 1 yr

Member at ELECTROMOS Sci-Tech Club ,IIT Bhilai, 2024 - 2025 · 1 yr

Education

Bachelor of Technology, Indian Institute of Technology, Bhilai

12th, Good Shepherd Convent, Shahdol

Parna Lata Chaurasia - Summer Research Intern in Bhilai | Tal