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Palimkota Yaswanth

Trainee | VLSI | Digital Physical Design Enthusiast | Learning Physical Implementation Flow|*Electronics & Communication Engineer | Recent Graduate*

India

1+ year of work experience

ICLabs IN
Jul 20251 yr 3 mosPresent

Bengaluru, Karnataka, India

"I am currently a trainee in VLSI, specializing in Digital Physical Design. I am learning the complete flow from floorplanning, placement, CTS, routing to signoff. Passionate about semiconductor design and eager to build a strong career in chip implementation. Looking forward to applying my knowledge in real-world projects and contributing to cutting-edge technologies."
Mar 20253 mosMay 2025

Chennai, Tamil Nadu, India

- NowPresent

❖ Physical design Flow implemented project: Picorv32 at 45nm (6424 Standard Cells, 7 Metal layers) based on PPA. ❖ Performed floor planning and power planning with rings/straps; achieved optimal core utilization and IR drop targets. ❖ Executed standard cell placement here analyzed cell congestion, density map and setup timing. ❖ Implemented Clock Tree Synthesis (CTS), reducing skew and latency for multi corner analysis. ❖ Completed global/detailed routing here analyzed types of routing congestion min spacing, min width, availability routing tracks. Checking DRC/LVS to support the signoff. ❖ Conducted Static Timing Analysis (STA) via Tempus: fixed setup/hold violations using VT swapping, buffering and cell sizing etc. For timing closure. ❖ In my design mostly optimized AREA and PERFORMANCE in 35 microns area in those tight constraints I achieved performance and I used techniques to satisfied the PPA.

Palimkota’s AI Stack

claude code
claude code
claude
claude
gemini
gemini
meta
meta
openai
openai

Education

Bachelor of Engineering, Electrical, Electronics and Communications Engineering

ARJUN COLLEGE OF TECHNOLOGY

20214 yrs2025
MGM

INTERMEDIATE

MGM

20192 yrs2021

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Headline

Trainee | VLSI | Digital Physical Design Enthusiast | Learning Physical Implementation Flow|*Electronics & Communication Engineer | Recent Graduate*

About

To obtain a challenging role in Electronics and Communication Engineering, utilizing skills in digital signal processing, communication systems, embedded systems and microcontrollers. Seeking to contribute to innovative projects and technologies in the field of ECE. Proficient in programming languages such as Python, C, and MATLAB. Looking to work with a team of professionals to design and develop cutting-edge electronic systems and solutions. Aiming to leverage my technical expertise to drive innovation and growth in the company

Location

India

AI stack

claude code

claude

gemini

meta

openai

Work experience

Trainee at ICLabs IN, Jul 2025 - Present · 1 yr 3 mos, Bengaluru, Karnataka, India, "I am currently a trainee in VLSI, specializing in Digital Physical Design. I am learning the complete flow from floorplanning, placement, CTS, routing to signoff. Passionate about semiconductor design and eager to build a strong career in chip implementation. Looking forward to applying my knowledge in real-world projects and contributing to cutting-edge technologies."

Trainee at ZF Commercial Vehicle Control Systems India Ltd, Mar 2025 - May 2025 · 3 mos, Chennai, Tamil Nadu, India

Design Internship at IC Labs, ❖ Physical design Flow implemented project: Picorv32 at 45nm (6424 Standard Cells, 7 Metal layers) based on PPA. ❖ Performed floor planning and power planning with rings/straps; achieved optimal core utilization and IR drop targets. ❖ Executed standard cell placement here analyzed cell congestion, density map and setup timing. ❖ Implemented Clock Tree Synthesis (CTS), reducing skew and latency for multi corner analysis. ❖ Completed global/detailed routing here analyzed types of routing congestion min spacing, min width, availability routing tracks. Checking DRC/LVS to support the signoff. ❖ Conducted Static Timing Analysis (STA) via Tempus: fixed setup/hold violations using VT swapping, buffering and cell sizing etc. For timing closure. ❖ In my design mostly optimized AREA and PERFORMANCE in 35 microns area in those tight constraints I achieved performance and I used techniques to satisfied the PPA.

Education

Bachelor of Engineering, Electrical, Electronics and Communications Engineering, ARJUN COLLEGE OF TECHNOLOGY

INTERMEDIATE, MGM

Palimkota Yaswanth - Trainee in India | Tal