Headline

ECE Engineer | VLSI · Embedded Systems · IoT | Interned at Emertxe · Ex-Google Student Ambassador | Open to Hardware/VLSI Roles

About

I design digital hardware. Not just on paper -in Verilog, on FPGA, with real timing constraints. I'm Pakeergowda R H, an ECE engineer at Bangalore Technological Institute (VTU), focused on VLSI Design, RTL Development, and Embedded Systems. While most students finish their degree with theory, I've been building: a 32-bit RISC Processor with a Vedic Multiplier and 64-bit MAC Unit -designed in Verilog, targeting FPGA implementation with high-performance, low-power architecture. What I've shipped and earned: → VLSI Design & Verification -certified by GUVI in collaboration with HCL & Google for Education. Covers RTL design, functional verification, and synthesis flows. → IoT Internship at Emertxe Information Technologies - hands-on embedded C, micro-controller programming, and SDLC-based project delivery. Completed March–April 2026. → 32-bit RISC Processor (active project) -full 5-stage pipeline in Verilog: fetch, decode, execute, memory, write-back. Integrating Vedic Multiplier for high-speed arithmetic in the 64-bit MAC Unit. FPGA target: Xilinx. → Google Student Ambassador (Gemini AI program) -selected from Bangalore Technological Institute for the Communique cohort, Dec 2025. → MongoDB Atlas certified -because chip designers who understand system-level data flows are rare. My technical stack: HDL: Verilog · (learning SystemVerilog) Tools: Xilinx Vivado · EDA basics . Systems: Embedded C · Microcontrollers · IoT Fundamentals: Digital Electronics · Computer Architecture · Signal Processing What I'm looking for: A VLSI Design internship where I can contribute to RTL coding, functional verification, or physical design -and learn from engineers building real silicon. If you're hiring ECE interns for VLSI/chip design roles, or know someone who is - let's connect. Bengaluru, Karnataka · Open to relocation rahulgowda9535@gmail.com

Location

Bengaluru

AI stack

antigravity

claude

gemini

openai

Bubble AI

ChatGPT

Work experience

VLSI Intern at SipQode, Jun 2026 - Jul 2026 · 2 mos, Bangalore Urban, Karnataka, India, Implemented a UART (Universal Asynchronous Receiver/Transmitter) Communication Protocol in Verilog HDL during my VLSI internship. Worked on the design and verification of core modules such as baud rate generator, UART TX/RX, FIFO buffers, and top-level UART integration. Explored concepts like asynchronous serial communication, oversampling, FSM-based RTL design, and verification using testbench simulations. This experience enhanced my practical understanding of digital communication protocols, RTL design flow, and VLSI implementation.

Intern at Emertxe Information Technologies, Mar 2026 - Apr 2026 · 2 mos, Bangalore Urban, Karnataka, India, • Completed a 7-week intensive IoT internship building foundational skills in C programming and micro-controller interfacing — one of 15 selected from BTI's cohort (EI26_015) • Developed SDLC-based IoT project from requirements through deployment, applying embedded systems programming with hands-on micro-controller hardware • Earned Certificate of Internship (Emertxe ID: EI26_015) covering IoT architecture, sensor integration, and real-time embedded system fundamentals

Google Student Ambassador for the Gemini AI program at Google Gemini, Jan 2025 - Dec 2025 · 1 yr, Bangalore, • Selected as a Google Student Ambassador for the Gemini AI program at Bangalore Technological Institute recognized for demonstrated enthusiasm, collaboration, and technical initiative • Represented BTI in Communique's Google Student Ambassador Program, participating in AI/ML-focused sessions and peer workshops • Earned Certificate of Participation (signed Dec 31, 2025) -one of the few ECE students selected from BTI for a program primarily targeting CS/IT peers

Education

Bachelor of Engineering, Electrical, Electronics and Communications Engineering, Visvesvaraya Technological University

Bangalore Technology institute ,Bangalore