Headline

Senior Design Verification Engineer @ACL Digital

About

✅With 4.8 years of experience and expertise in IP-level verification. ✅Proficient in the System Verilog and UVM methodology. ✅Hands-on experience in developing the Testbench (TB) and its components for IP level verification in a UVM environment. ✅Skilled in creating meticulous test plans, creating diverse test cases and running regression tests. ✅Expertise in code and functional coverage analysis ✅Worked on Assertion-based verification. ✅Regression flow in NBFLOW ✅Tools used : synopsys and verdi.

Location

Bengaluru

AI stack

claude code

codex

gemini

openai

ChatGPT Images

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Work experience

Senior Design Verification Engineer at ACL Digital, Jul 2025 - Present · 1 yr 3 mos, Bengaluru, Karnataka, India

Design Verification Engineer at Tech Mahindra, Mar 2022 - Jun 2025 · 3 yrs 4 mos, Bengaluru, Karnataka, India, - Worked on IP verification and implemented the test cases. - Contribute on code and functional coverage. - Developed the assertions. -UVM RAL based verification for register modelling and access.

Trainee at VLSI FIRST, Sep 2021 - Feb 2022 · 6 mos, Hyderabad, Telangana, India, - Worked on SPI protocol. -Proficient in Verilog, System Verilog and UVM. -Knowledge on AMBA protocols.

Education

B.Tech, Electronics and Communications Engineering, Gudlavalleru Engineering College, Seshadri Rao Knowledge Village, Gudlavalleru, PIN-521356(CC-48)