---
title: "Niyathi Rumala - ASIC Design Engineer in Bengaluru | Tal"
description: "Meet Niyathi Rumala, ASIC Design Engineer | VLSI Design Flow: RTL to GDS based in Bengaluru."
image: "https://tal.club/meet/niyathi-rumala/share-image"
---

# Niyathi Rumala on Tal

## Headline

ASIC Design Engineer \| VLSI Design Flow: RTL to GDS

## About

As an ASIC Design Engineer at Cyient, I apply my expertise in VLSI and Embedded Systems to design and develop complex digital circuits for various applications\. I have a Master of Engineering degree from Chaitanya Bharathi Institute Of Technology, where I specialized in VLSI & Embedded Systems\. I also hold a certification from Nptel, IIIT Delhi, in Vlsi Design Flow: RTL to GDS\. My skills include Tcl\-Tk, Linux, and Verilog, which enable me to work efficiently and effectively in a team environment\. I am passionate about learning new technologies and staying updated with the latest trends in the field\. I am always eager to take on new challenges and contribute to the success of the organization\.

## Location

Bengaluru

## Work experience

ASIC Design Engineer at Cyient, Jun 2021 \- Nov 2022 · 1 yr 6 mos, Hyderabad, Telangana, India

## Education

Certification, Vlsi Design Flow: RTL to GDS, Nptel, IIIT Delhi

Master of Engineering \- MEng, VLSI & Embedded Systems, Chaitanya Bharathi institute of technology

[View the original profile](https://tal.club/meet/niyathi-rumala)

```json
{
  "@context": "https://schema.org",
  "@graph": [
    {
      "@type": "Person",
      "@id": "https://tal.club/meet/niyathi-rumala#person",
      "name": "Niyathi Rumala",
      "url": "https://tal.club/meet/niyathi-rumala",
      "description": "Meet Niyathi Rumala, ASIC Design Engineer | VLSI Design Flow: RTL to GDS based in Bengaluru.",
      "jobTitle": "ASIC Design Engineer",
      "worksFor": {
        "@type": "Organization",
        "name": "Cyient"
      },
      "hasOccupation": {
        "@type": "Occupation",
        "name": "ASIC Design Engineer"
      },
      "homeLocation": {
        "@type": "Place",
        "name": "Bengaluru"
      },
      "alumniOf": [
        {
          "@type": "EducationalOrganization",
          "name": "Nptel, IIIT Delhi"
        },
        {
          "@type": "EducationalOrganization",
          "name": "Chaitanya Bharathi institute of technology"
        }
      ],
      "mainEntityOfPage": {
        "@id": "https://tal.club/meet/niyathi-rumala#webpage"
      }
    },
    {
      "@type": "ProfilePage",
      "@id": "https://tal.club/meet/niyathi-rumala#webpage",
      "url": "https://tal.club/meet/niyathi-rumala",
      "name": "Niyathi Rumala on Tal",
      "description": "Meet Niyathi Rumala, ASIC Design Engineer | VLSI Design Flow: RTL to GDS based in Bengaluru.",
      "dateModified": "2026-06-10T13:55:45.505Z",
      "isPartOf": {
        "@id": "https://tal.club/#website"
      },
      "mainEntity": {
        "@id": "https://tal.club/meet/niyathi-rumala#person"
      },
      "inLanguage": "en-IN"
    }
  ]
}
```