ASIC Design Engineer | VLSI Design Flow: RTL to GDS
Hyderabad, Telangana, India
Certification, Vlsi Design Flow: RTL to GDS
Nptel, IIIT Delhi
Master of Engineering - MEng, VLSI & Embedded Systems
Chaitanya Bharathi institute of technology
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As an ASIC Design Engineer at Cyient, I apply my expertise in VLSI and Embedded Systems to design and develop complex digital circuits for various applications. I have a Master of Engineering degree from Chaitanya Bharathi Institute Of Technology, where I specialized in VLSI & Embedded Systems. I also hold a certification from Nptel, IIIT Delhi, in Vlsi Design Flow: RTL to GDS. My skills include Tcl-Tk, Linux, and Verilog, which enable me to work efficiently and effectively in a team environment. I am passionate about learning new technologies and staying updated with the latest trends in the field. I am always eager to take on new challenges and contribute to the success of the organization.
Bengaluru
ASIC Design Engineer at Cyient, Jun 2021 - Nov 2022 · 1 yr 6 mos, Hyderabad, Telangana, India
Certification, Vlsi Design Flow: RTL to GDS, Nptel, IIIT Delhi
Master of Engineering - MEng, VLSI & Embedded Systems, Chaitanya Bharathi institute of technology