Headline

Bridging Circuits & Code |RTL Design & Verification Engineer skilled in UVM, SystemVerilog & RTL Debug | VLSI Design and verification Trainee at IIIT Bangalore

About

Passionate VLSI Design & Verification enthusiast, trained at IIIT Bangalore’s KVLSI program. Skilled in RTL design, Verilog, System Verilog, ASIC/FPGA, and EDA tools (Cadence, Model Sim) with hands-on projects in Turbo Decoder, FIFO design. Driven to innovate and optimize digital systems in the semiconductor industry.

Location

Bangalore Urban

AI stack

claude code

codex

openai

Work experience

KVLSI at International Institute of Information Technology Bangalore, Jan 2025 - Present · 1 yr 9 mos

Data Analyst at Main Flow Services and Technologies Pvt. Ltd., Nov 2024 - Feb 2025 · 4 mos, Experienced in using Python (Pandas, NumPy, ) to clean, analyze, and visualize data, extracting insights to inform business decisions. Proficient in querying databases (SQL) and building statistical models to solve real-world problems. Adept at communicating findings clearly through reports and presentations

Education

Post Graduate Diploma, Vlsi Design and verification, International Institute of Information Technology Bangalore

Bachelor of Engineering - BE, Electronic and communication Engineering, Visvesvaraya Technological University