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Nithin

Senior Engineer at Bosch Global Software Technologies

Udupi

5+ years of work experience

Bosch Global Software Technologies
Jan 20242 yrs 7 mosPresent

Bengaluru

Bosch Global Software Technologies
Jul 20221 yr 6 mosDec 2023

Bengaluru, Karnataka, India

Bosch Global Software Technologies
Sep 202111 mosJul 2022

Bengaluru, Karnataka, India

KarMic Design Private Ltd
Feb 20216 mosJul 2021

Manipal, Karnataka

KarMic Design Private Ltd
May 20192 mosJun 2019

Manipal, Karnataka

Project training on "Phase Frequency Detector (PFD)" which is an integral part of Phase Locked Loop(PLL) using Cadence Virtuoso. Designed and simulated the layout of various cells like basic gates, flip flops and PFD using Cadence Virtuoso [180nm technology (gpdk 180)]. -> Learnt ASIC design flow, working of MOSFET, CMOS logic implementation in VLSI. -> Understood the working of PLL, PFD , Flip-Flops and basic gates. -> Learnt efficient layout design practices -> Hands on experience in Schematic Design Simulation, Layout designing steps like Placement, Routing, DRC and LVS verification of Phase frequency detector using Cadence tools.

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Education

Manipal institute of technology

Bachelor of Technology - BTech, Electronics and Communications Engineering

Manipal institute of technology

20174 yrs2021

Pre-University

Mahatma Gandhi Memorial College, Udupi - 576102

20152 yrs2017

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Headline

Senior Engineer at Bosch Global Software Technologies

Location

Udupi

AI stack

cursor

github copilot

notion

ollama

Work experience

Senior Engineer at Bosch Global Software Technologies, Jan 2024 - Present · 2 yrs 7 mos, Bengaluru

Software Engineer at Bosch Global Software Technologies, Jul 2022 - Dec 2023 · 1 yr 6 mos, Bengaluru, Karnataka, India

Associate Software Engineer at Bosch Global Software Technologies, Sep 2021 - Jul 2022 · 11 mos, Bengaluru, Karnataka, India

Internship Trainee at KarMic Design Private Ltd, Feb 2021 - Jul 2021 · 6 mos, Manipal, Karnataka

VLSI Design Intern at KarMic Design Private Ltd, May 2019 - Jun 2019 · 2 mos, Manipal, Karnataka, Project training on "Phase Frequency Detector (PFD)" which is an integral part of Phase Locked Loop(PLL) using Cadence Virtuoso. Designed and simulated the layout of various cells like basic gates, flip flops and PFD using Cadence Virtuoso [180nm technology (gpdk 180)]. -> Learnt ASIC design flow, working of MOSFET, CMOS logic implementation in VLSI. -> Understood the working of PLL, PFD , Flip-Flops and basic gates. -> Learnt efficient layout design practices -> Hands on experience in Schematic Design Simulation, Layout designing steps like Placement, Routing, DRC and LVS verification of Phase frequency detector using Cadence tools.

Education

Bachelor of Technology - BTech, Electronics and Communications Engineering, Manipal institute of technology

Pre-University, Mahatma Gandhi Memorial College, Udupi - 576102

Nithin - Senior Engineer in Udupi | Tal