---
title: "Nikita Burse - Design and verification Engineer in Bengaluru | Tal"
description: "Meet Nikita Burse, VLSI Design & Verification Engineer | SystemVerilog | UVM | Verilog | Functional Verification | APB | AXI | AHB | SVA | Open to Work based in Bengaluru. AI stack includes gemini."
image: "https://tal.club/meet/nikita-burse/share-image"
---

# Nikita Burse on Tal

## Headline

VLSI Design & Verification Engineer \| SystemVerilog \| UVM \| Verilog \| Functional Verification \| APB \| AXI \| AHB \| SVA \| Open to Work

## About

Electronics and Telecommunication Engineering graduate with a strong interest in VLSI Design and Verification\. Hands\-on experience in Verilog, SystemVerilog, UVM, Functional Verification and SVA\. Worked on RTL design and verification projects involving APB, SPI, AXI and AHB protocols, including testbenches, drivers, monitors and scoreboards\. Seeking entry\-level opportunities in VLSI Design Verification, RTL Design and Functional Verification

## Location

Bengaluru

## AI stack

gemini

## Work experience

Design and verification Engineer at Maven Silicon, Sep 2025 \- Present · 1 yr 2 mos, Bengaluru

Electronics Intern – LED Display Technology at Aura Opto Electronics India Pvt Ltd\., Dec 2024 \- Apr 2025 · 5 mos, Nashik

## Education

Bachelor of Engineering \- Btech, Electronic and telecommunications engineering, Walchand Institute of Technology, Solapur

HSC, TOSHNIWAL ARTS, COMMERCE & SCIENCE COLLEGE, SENGAON

[View the original profile](https://tal.club/meet/nikita-burse)

```json
{
  "@context": "https://schema.org",
  "@graph": [
    {
      "@type": "Person",
      "@id": "https://tal.club/meet/nikita-burse#person",
      "name": "Nikita Burse",
      "url": "https://tal.club/meet/nikita-burse",
      "image": "https://tal.club/meet/nikita-burse/profile-photo.jpg",
      "description": "Meet Nikita Burse, VLSI Design & Verification Engineer | SystemVerilog | UVM | Verilog | Functional Verification | APB | AXI | AHB | SVA | Open to Work based in Bengaluru. AI stack includes gemini.",
      "jobTitle": "Design and verification Engineer",
      "worksFor": {
        "@type": "Organization",
        "name": "Maven Silicon"
      },
      "hasOccupation": {
        "@type": "Occupation",
        "name": "Design and verification Engineer"
      },
      "homeLocation": {
        "@type": "Place",
        "name": "Bengaluru"
      },
      "alumniOf": [
        {
          "@type": "EducationalOrganization",
          "name": "Walchand Institute of Technology, Solapur"
        },
        {
          "@type": "EducationalOrganization",
          "name": "TOSHNIWAL ARTS, COMMERCE & SCIENCE COLLEGE, SENGAON"
        }
      ],
      "knowsAbout": [
        "gemini"
      ],
      "mainEntityOfPage": {
        "@id": "https://tal.club/meet/nikita-burse#webpage"
      }
    },
    {
      "@type": "ProfilePage",
      "@id": "https://tal.club/meet/nikita-burse#webpage",
      "url": "https://tal.club/meet/nikita-burse",
      "name": "Nikita Burse on Tal",
      "description": "Meet Nikita Burse, VLSI Design & Verification Engineer | SystemVerilog | UVM | Verilog | Functional Verification | APB | AXI | AHB | SVA | Open to Work based in Bengaluru. AI stack includes gemini.",
      "dateModified": "2026-10-01T17:32:14.516Z",
      "isPartOf": {
        "@id": "https://tal.club/#website"
      },
      "mainEntity": {
        "@id": "https://tal.club/meet/nikita-burse#person"
      },
      "primaryImageOfPage": {
        "@type": "ImageObject",
        "url": "https://tal.club/meet/nikita-burse/profile-photo.jpg",
        "contentUrl": "https://tal.club/meet/nikita-burse/profile-photo.jpg",
        "caption": "Nikita Burse profile photo on Tal"
      },
      "inLanguage": "en-IN"
    }
  ]
}
```