---
title: "Naveen A - Student Intern in Greater Chennai Area | Tal"
description: "Meet Naveen A, RTL Design & Verification Engineer | Synopsys/Samsung ISWDP Fellow | Verilog · SystemVerilog · UVM | RISC-V · FPGA · ASIC | Synopsys VCS · Verdi . FC | Cadence Virtuoso | SIH ’25 Finalist | Pre-Final Year @ RIT, Chennai based in Greater Chennai Area. AI stack includes hugging face, o..."
image: "https://tal.club/meet/naveen-a/share-image"
---

# Naveen A on Tal

## Headline

RTL Design & Verification Engineer \| Synopsys/Samsung ISWDP Fellow \| Verilog · SystemVerilog · UVM \| RISC\-V · FPGA · ASIC \| Synopsys VCS · Verdi \. FC \| Cadence Virtuoso \| SIH ’25 Finalist \| Pre\-Final Year @ RIT, Chennai

## About

I build digital hardware from scratch — processors, accelerators, game engines — all in RTL\. My current project is a 5\-stage pipelined RV32I processor in Verilog\. Full forwarding unit, flush logic, hazard resolution across EX and MEM stages — 19 modules, \~765 lines of RTL, simulated at 10 MHz\. Before that, a single\-cycle RV32I core supporting 12 base integer instructions across R, I, S, and B types — ALU, register file, control logic, datapath, all from scratch\. Before that, a Space Invaders clone with a custom VGA sprite engine on Altera DE2 — 640×480 output, debounced controls, game\-state FSM — entirely in RTL, no software layer in between\. On the verification side, I write testbenches, trace signals, and find the bugs that compile cleanly and simulate quietly — until they don't\. Currently working through UVM methodology with Synopsys VCS and Verdi as my primary debug environment\. EDA Stack: Synopsys — VCS · Verdi · Fusion Compiler · SpyGlass · Custom Compiler · PrimeWave Cadence — Virtuoso Open Source — Icarus Verilog · Verilator · GTKWave · Yosys · OpenLane · Qflow · OpenROAD Credentials: Synopsys/Samsung ISWDP Cohort 7 Fellow Smart India Hackathon — National Finalist IIT PALS InnoWAH 2025–26 — Runner Up CGPA 8\.78 — Rajalakshmi Institute of Technology I've also worked across embedded systems — LiDAR driver firmware in Embedded C on TI hardware with interrupt\-driven UART at 115200 baud and a custom ring buffer parser, IoT sensor pipelines on Raspberry Pi 5 and ESP32, edge compute with Azure integration\. Different domain, same instinct: understand the hardware first, then build on top of it\. The bug that only shows up 10,000 clock cycles in? That's the interesting one\. Currently in my pre\-final year, graduating 2027\. Open to internships and full\-time roles in RTL Design, Functional Verification, and FPGA Engineering — India and beyond\. GitHub: github\.com/Navnofficial

## Location

Greater Chennai Area

## AI stack

hugging face

ollama

openai

replit

## Work experience

Student Intern at Struent Semiconductors Private Limited, Apr 2026 \- Present · 2 mos, Chennai, Tamil Nadu, India, Developing self\-checking SystemVerilog testbenches for ASIC digital designs — covering combinational and sequential logic from gate\-level to processor\-level verification\. Working on UART protocol\-based RTL verification, tracing signal behavior through GTKWave and validating functional correctness using Icarus Verilog and Verilator on EDA Playground\.

Project Intern at Susan Future Technologies, Oct 2025 \- Jan 2026 · 4 mos, Chennai, Tamil Nadu, India, Solely engineered a modular LiDAR driver in Embedded C on TI TM4C123 — interrupt\-driven UART at 115200 baud, custom ring buffer parser, and single\-range command protocol interfacing LiDAR for real\-time distance acquisition\. Implemented 2D LiDAR scanning pipeline achieving 70–90% range accuracy, forming the sensing foundation for a LiDAR\-based spatial mapping system

Student Intern at Spinacle, Feb 2025 \- Oct 2025 · 9 mos, Chennai, Tamil Nadu, India

Research And Development Intern at Spinacle, Jan 2025 \- May 2025 · 5 mos, Chennai, Tamil Nadu, India, Designed and deployed a multi\-sensor IoT monitoring system on Raspberry Pi 5 and ESP32 — integrating DHT11, pH, and pressure sensors for real\-time gut\-health bio\-data acquisition at \~10K data points per second\. Built and validated a Microsoft Azure Cloud pipeline for scalable storage and data management, delivering a functional MVP prototype for client evaluation\.

Student Ambassador – Center of IoT at Rajalakshmi Institute of Technology, Sep 2024 \- Jun 2025 · 10 mos, Chennai, Tamil Nadu, India, • Representing the Center of IoT in organizing and promoting IoT\-based workshops, events, and innovation challenges \. • Collaborating with faculty and peers to spread awareness of IoT applications and industry trends\.

Project Intern at Spinacle, Apr 2024 \- May 2024 · 2 mos, Built an ESP32\-based real\-time audio capture system using INMP441 MEMS microphone and Pi Camera Module 3, with on\-device data collection pipeline and Azure Cloud upload for audio and visual data storage\. Architected end\-to\-end data flow for AI\-driven anomaly detection — from sensor capture to cloud ingestion — laying the inference pipeline foundation for production deployment\.

## Education

Bachelor of Engineering \- BE, Electrical and Electronics Engineering \(VLSI Design and Technology\), Rajalakshmi Institute of Technology

## Public links

- github: https://github\.com/Navnofficial

[View the original profile](https://tal.club/meet/naveen-a)

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