--- title: "Nampally Sai Rukmangad Rohit - Analog Design Engineer in Bengaluru | Tal" description: "Meet Nampally Sai Rukmangad Rohit, Analog Design Engineer | VLSI Specialist | CMOS, Pad Circuits, Cadence Virtuoso | Driving Semiconductor Innovations based in Bengaluru. AI stack includes claude, deepseek, and gemini." image: "https://tal.club/meet/nampally-sai-rukmangad-rohit/share-image" --- # Nampally Sai Rukmangad Rohit on Tal ## Headline Analog Design Engineer \| VLSI Specialist \| CMOS, Pad Circuits, Cadence Virtuoso \| Driving Semiconductor Innovations ## About I'm an Analog/Mixed\-Signal IC Design Engineer with 2\+ years of industry experience designing production\-grade AMS IPs across 12 nm to 40 nm technology nodes at L&T Semiconductor Technologies and Infineon Technologies\. My core work spans Power\-on Reset \(POR\), Bandgap Reference \(BGR\), LDO verification, Crystal Oscillator \(32 kHz RTC\), Glitch Filters, and Over\-Voltage\-Tolerance \(OVT\) circuits β€” from schematic through post\-layout \(PEX\) and tape\-out readiness\. At Infineon, I designed 3\.3V GPIO IO circuits \(200 MHz\) including Output Buffers, Schmitt Triggers, and OVT pads β€” validated through Monte Carlo and Corner Analysis in Cadence Virtuoso ADE XL\. I hold an M\.Tech in VLSI Design from NIT Delhi and have published research on low\-power CMOS design at an international conference in Thailand\. πŸ“Currently Based in Bengaluru \| DM me or reach out at rukmangadrohit@gmail\.com ## Location Bengaluru ## AI stack claude deepseek gemini kimi notebooklm perplexity ## Work experience Analog Design Engineer at L&T Semiconductor Technologies, Sep 2024 \- Present Β· 2 yrs 1 mo, Bengaluru, Karnataka, India, IP Developement \- OTD β†’ Currently under development of Over temperature Detection module for variations in Temperature to protect the IC from freezing and heating β†’ Technology is 12nm FinFet based technology\. IP DEVELOPMENT \- POR Circuit β†’ Developed a power on reset in 12nm FinFet Technology β†’ The circuit is robust for kinds of power profiles\. IP Development – Real Time Clock \(RTC\) β†’ Designed and developed a Real Time Clock operating at 32,768 Hz in 22 nm FDSOI CMOS technology\. β†’ Developed key sub\-blocks including: β†’ Beta Multiplier for stable current reference generation\. β†’ gm\-Amplifier for precise sinusoidal signal amplification\. β†’ Waveform Generators for square wave output\. β†’ Automatic Loop Control \(ALC\) for dynamic oscillator stability\. β†’ Counter Block for accurate timekeeping and frequency division\. β†’ Optimized the RTC design for low power, high stability, and robust operation across PVT \(process\-voltage\-temperature\) variations\. Project – Power\-On Reset Circuit β†’ Designed a Power\-On Reset \(POR\) circuit in 12 nm LPP FinFET technology \(GF12\)\. β†’ Ensured reliable system initialization with a fast\-response, accurate reset mechanism across PVT variations\. β†’ Focused on low area and low\-power design while meeting stringent FinFET constraints\. Technical Tools & Methodologies β†’ Technology nodes: 22 nm FDSOI CMOS, 12 nm FinFET\. β†’ Design & simulation: Cadence Virtuoso, ADE XL, Spectre\. β†’ Performed Monte Carlo, Corner, and Transient analyses for performance and reliability verification\. β†’ Applied best practices in analog IP design, including noise optimization, power efficiency, and signal integrity enhancement\. Analog Design Engineer at Infineon Technologies, Jul 2023 \- May 2024 Β· 11 mos, Bengaluru, Karnataka, India, Analog I/O Design Engineer Intern – Mixed Signal Design Department β†’ GPIO Design & Implementation: Designed and implemented 3\.3 V GPIO pins operating at pulse frequencies up to 200 MHz\. β†’ Design Challenges: Addressed fail\-safe mechanisms and over\-voltage tolerance for 1 MHz pulses, ensuring robust performance under challenging conditions\. β†’ Output Buffer Development: Developed Level Shifter sub\-blocks, Tri\-state buffers, Pre\-drivers, and Drivers to support pulse specifications of 100 MHz and 200 MHz\. β†’ Input Buffer Development: Engineered Schmitt Trigger circuits with 300 mV hysteresis sweep, down\-conversion blocks, and input buffers for reliable signal reception\. β†’ Over\-Voltage Protection: Designed and implemented protection circuits at the GPIO pad level, safeguarding against voltages above 3\.3 V up to a maximum of 5 V\. β†’ Performance Optimization: Successfully created circuits capable of operating across a broad frequency range \(5 MHz to 200 MHz\), enhancing overall reliability and robustness\. β†’ Technical Tools & Methodologies: Utilized 40 nm technology node with Cadence Virtuoso and ADE XL for design and simulation\. Performed Monte Carlo and Corner analyses to validate circuit performance under process, voltage, and temperature variations\. Intern at Bharat Dynamics Limited, Jan 2019 \- Mar 2019 Β· 3 mos, Learnt a lot\. People over there are good & are full of Knowledge\. Intern at IOT Gyan SMART BRIDGE at Nacharam \., Jun 2018 \- Jun 2018 Β· 1 mo, Greater Hyderabad Area, The Intern was on ESP 32 and STM 32 Under Embedded IOT\. Intern at RCI, May 2018 \- Jun 2018 Β· 2 mos, India, The intern was on Technical study on Inertial Navigation System and GPS in ROCKETS ## Education Master of Technology \- MTech, Electronics and Communication Engineering with Specialisation in VLSI, National institute of technology delhi Bachelor of Technology, Electronics communications and engineering, sreenidhi institute of science and technology [View the original profile](https://tal.club/meet/nampally-sai-rukmangad-rohit) ```json { "@context": "https://schema.org", "@graph": [ { "@type": "Person", "@id": "https://tal.club/meet/nampally-sai-rukmangad-rohit#person", "name": "Nampally Sai Rukmangad Rohit", "url": "https://tal.club/meet/nampally-sai-rukmangad-rohit", "image": "https://tal.club/meet/nampally-sai-rukmangad-rohit/profile-photo.jpg", "description": "Meet Nampally Sai Rukmangad Rohit, Analog Design Engineer | VLSI Specialist | CMOS, Pad Circuits, Cadence Virtuoso | Driving Semiconductor Innovations based in Bengaluru. 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